Memory array with reduced read power requirements and increased capacity

An electronic memory array, comprising:

• a plurality of memory domains, each memory domain including a plurality of rows of bit cells and a plurality of columns of bit cells;
• a current controller including a current controller output electrically connectable to said plurality of memory domains and configured to control a bit cell current;
• and
• a selector device electrically connected to said current controller and said plurality of memory domains, said selector device configured to selectively electrically connect said current controller output to only a select one of said memory domains, such that said current controller controls only said bit cell current of said bit cells of said select memory domain,
• wherein said selector device includes a demultiplexer including a demultiplexer input electrically connected to said current controller output and a plurality of demultiplexer outputs,
• wherein each demultiplexer output is electrically connected to a corresponding one of said memory domains, and
• wherein each demultiplexer output is electrically connectable to each column of bit cells of said corresponding memory domain.