Semiconductor devices
AssigneeSK hynix Inc.
InventorMin Seok Choi
Life of this patent
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Abstract
A semiconductor device includes a bank address generation circuit, a row/column address generation circuit, and an operation control circuit. The bank address generation circuit generates a bank address signal according to a bank group selection signal which is generated in response to a first temperature code and a second temperature code. The row/column address generation circuit generates a row address signal and a column address signal according to an area selection signal which is generated in response to a third temperature code and a fourth temperature code. The operation control circuit performs a data scrub operation on a cell which is accessed by the bank address signal, the row address signal and the column address signal.
Claims17
A semiconductor device comprising:
- a bank address generation circuit configured to generate a bank address signal according to a bank group selection signal which is generated in response to a first temperature code and a second temperature code;
- a row/column address generation circuit configured to generate a row address signal and a column address signal according to an area selection signal which is generated in response to a third temperature code and a fourth temperature code;
- and
- an operation control circuit configured to perform a data scrub operation on a cell which is accessed by the bank address signal, the row address signal, and the column address signal, wherein the row/column address generation circuit outputs the row address signal and the column address signal in which each are counted in synchronization with an operation clock signal whose frequency is determined in response to the third temperature code and the fourth temperature code.
A semiconductor device comprising:
- a row/column address generation circuit configured to generate a row address signal and a column address signal according to an area selection signal which is generated in response to a first temperature code and a second temperature code and according to a refresh signal;
- and
- an operation control circuit configured to perform a data scrub operation on a cell which is accessed by a bank address signal, the row address signal, and the column address signal, wherein the row/column address generation circuit outputs the row address signal and the column address signal in which each are counted in synchronization with an operation clock signal whose frequency is determined in response to the first temperature code and the second temperature code.
Dependencies are inferred from the claim text.