Host and multi-display system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsByung Tak Lee, Kyoung Man Kim, Jong Ho Roh
Life of this patent
Estimating the term…
Abstract
A system on chip (SoC) for transmitting data packets to a display driver integrated circuit (IC) controlling a plurality of displays is provided. The SoC includes a first register, and a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays. A tearing effect (TE) signal detection circuit is configured to detect a TE signal output from the display driver IC. A data transmission circuit is configured to generate a plurality of frame rate adjustment signals using the detected TE signal and the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals.
Claims20
A system on chip (SoC) for transmitting data packets to a display driver integrated circuit (IC) configured to control a plurality of displays, the system on chip comprising:
- a first register;
- a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays;
- a tearing effect (TE) signal detection circuit configured to detect a TE signal output from the display driver IC and indicating a display status of at least one of the plurality of displays;
- and
- a data transmission circuit configured to generate a plurality of frame rate adjustment signals by adjusting a period of the detected TE signal in response to the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals, respectively.
A multi-display system, comprising:
- a display driver integrated circuit (IC) configured to control operations of a plurality of displays;
- a high-speed serial interface;
- and
- a processor configured to sequentially transmit data packets to the display driver IC through the high-speed serial interface, the processor including:
- a first register,
- a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays,
- a tearing effect (TE) signal detection circuit configured to detect a TE signal output from the display driver IC and indicating a display status of at least one of the plurality of displays, and
- a data transmission circuit configured to generate a plurality of frame rate adjustment signals by adjusting a period of the detected TE signal in response to the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals.
A multi-display system, comprising:
- a display driver integrated circuit (IC) configured to control operations of a plurality of displays;
- and
- a processor configured to sequentially transmit data packets to the display driver IC through a high-speed serial interface;
- wherein the display driver IC is configured to decode a first identifier included in a first data packet among the data packets received through the high-speed serial interface, identify one of the displays according to decoding result, and transmit first data included in the first data packet to the identified display.
Dependencies are inferred from the claim text.