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US 10,096,302 B2Granted
Display system
AssigneeSamsung Electronics Co., Ltd.
InventorsJong Ho Roh, Bong Il Park
Life of this patent
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Abstract
A display system is provided. The display system includes a perframe controller configured to receive a frame synchronization signal and to change values of M and N in synchronization with at least one pulse of the frame synchronization signal, where M and N are natural numbers; and a fractional divider configured to generate and output a pixel clock signal by dividing an input clock signal by a division ratio of N/M.
Claims11
A device for controlling a display system, the device comprising:
- a memory comprising a first lookup table (LUT) including a plurality of entries, where each entry includes a frame number of a corresponding one of a plurality of sequential frames, a first value, and a second value and where the first and second values are natural numbers;
- a controller configured to count at least one pulse of a received vertical synchronization (VSYNC) signal to obtain a frame number that corresponds to one of the plurality of sequential frames, access one of the entries of the first LUT using the obtained frame number to obtain the corresponding first and second values, and change a value of M to the obtained first value and change a value of N to the obtained second value in synchronization with a pulse of the received VSYNC signal;
- a fractional divider configured to generate and output a pixel clock signal by dividing an input clock signal by a division ratio of the changed value of N to the changed value of M;
- and
- a display controller configured to adjust a frame rate of the display system according to the pixel clock signal, wherein the frame rate is a certain number of frames per second calculated by multiplying the changed value of N by the changed value of M and dividing a result of the multiplying by 60.
2 more elements
A display system comprising:
- a display device configured to display images only outside a period while a pulse occurs within a vertical synchronization (VSYNC) signal;
- a first controller configured to generate the VSYNC signal and output image data to the display device according to a pixel clock signal;
- a second controller that is configured to count at least one pulse of the VSYNC signal to obtain a frame number that corresponds to one of a plurality of sequential frames, retrieve a first value and a second value from an entry in a lookup table corresponding to the obtained frame number, and change a value of N to the retrieved first value and change a value of M to the retrieved second value, where the retrieved first and second values are natural numbers;
- and
- a fractional divider configured to divide an input clock signal by a division ratio of the changed value of N to the changed value of M only within the period to generate the pixel clock signal,
- wherein the first controller is configured to adjust a frame rate of the display system according to the pixel clock signal, wherein the frame rate is a certain number of frames per second calculated by multiplying the changed value of N by the changed value of M and dividing a result of the multiplying by 60.
3 more elements
Dependencies are inferred from the claim text.