Gate driver and liquid crystal display
AssigneeShenzhen China Star Optoelectronics Technology Co., Ltd.
InventorPeng Du
Life of this patent
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Abstract
The present invention proposes a gate driver including a plurality of gate driver on array (GOA) units. Each of the GOA unit includes a main driving circuit, a starting signal output circuit, and a plurality of gate driving circuits. The gate driver utilizes a starting signal and two inversed clock signals to control the charging period and the discharging period of the gate driver. Furthermore, the gate driver utilizes multiple clock signals to control the output of the gate driving signals. In this way, the number of the clock signals is reduced and thus the power consumption is also reduced.
Claims16
A gate driver comprising a plurality of gate driver on array (GOA) units, each of the GOA units comprising:
- a main driving circuit, comprising:
- a first transistor, comprising a source, a drain, and a gate, wherein the source of the first transistor is configured to receive a starting signal and the gate of the first transistor is configured to receive a first triggering clock signal;
- a second transistor, comprising a source, a drain, and a gate, wherein the gate of the second transistor is configured to receive a second triggering clock signal;
- and
- a third transistor, comprising a source, a drain, and a gate,
- wherein the main driving circuit has a first control node and a second control node and is configured to generate a charging signal on the first control node and generate a control signal on the second control node in response to the starting signal, the first triggering clock signal and the second clock signal;
- a starting signal output circuit, comprising:
- a fourth transistor, configured to receive the charging signal to output an intermediate signal;
- and
- a fifth transistor, configured to receive the control signal to deactivate the intermediate signal;
- and
- a plurality of gate driving circuits, each of the gate driving circuit comprising:
- a sixth transistor, configured to receive the charging signal to output a gate driving signal;
- and
- a seventh transistor, configured to receive the control signal to deactivate the gate driving signal,
- wherein the main driving circuit further comprises an eighth transistor, a ninth transistor, and a tenth transistor, and wherein when the first transistor is turned on by the first triggering clock signal, the eighth transistor, the ninth transistor, and the tenth transistor are turned on such that the charging signal is generated on the first control node and the control signal is generated on the second control node.
A liquid crystal display comprising a gate driver, the gate driver comprising a plurality of gate driver on array (GOA) units, each of the GOA units comprising:
- a main driving circuit, comprising:
- a first transistor, comprising a source, a drain, and a gate, wherein the source of the first transistor is configured to receive a starting signal and the gate of the first transistor is configured to receive a first triggering clock signal;
- a second transistor, comprising a source, a drain, and a gate, wherein the gate of the second transistor is configured to receive a second triggering clock signal;
- and
- a third transistor, comprising a source, a drain, and a gate,
- wherein the main driving circuit has a first control node and a second control node and is configured to generate a charging signal on the first control node and generate a control signal on the second control node in response to the starting signal, the first triggering clock signal and the second clock signal;
- a starting signal output circuit, comprising:
- a fourth transistor, configured to receive the charging signal to output an intermediate signal;
- and
- a fifth transistor, configured to receive the control signal to deactivate the intermediate signal;
- and
- a plurality of gate driving circuits, each of the gate driving circuit comprising:
- a sixth transistor, configured to receive the charging signal to output a gate driving signal;
- and
- a seventh transistor, configured to receive the control signal to deactivate the gate driving signal,
- wherein the main driving circuit further comprises an eighth transistor, a ninth transistor, and a tenth transistor, and wherein when the first transistor is turned on by the first triggering clock signal, the eighth transistor, the ninth transistor, and the tenth transistor are turned on such that the charging signal is generated on the first control node and the control signal is generated on the second control node.
Dependencies are inferred from the claim text.