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US 10,096,078 B2Granted
Multi GPU interconnect techniques
AssigneeNVIDIA Corporation
InventorsMing Yan, Chao Chen
Life of this patent
Estimating the term…
Abstract
A graphics processing subsystem includes one or more memory devices and two or more graphics processing units (GPU). The graphics processing units each include a memory interface. A first sub-set of the memory interface of the first graphics processing unit communicatively couples the first graphics processing unit to the first memory device. A first sub-set of the memory interface of the second graphics processing unit is connected to a second sub-set of the memory interface of the first graphics processing unit.
Claims14
A device comprising:
- a first memory device;
- a first graphics processing unit including a memory interface, wherein a first sub-set of the bit width of communication links of the memory interface of the first graphics processing unit communicatively couples the first graphics processing unit to the first memory device;
- and
- a second graphics processing unit including a memory interface, wherein a first sub-set of the bit width of communication links of the memory interface of the second graphics processing unit is connected to a second sub-set of the bit width of the communication links of the memory interface of the first graphics processing unit, wherein the combined bit width of first and second sub-set of the bit width of communication links of the memory interface of the first graphics processing unit is equal to the total bit width of the communication links of the memory interface of the first graphics processing unit.
1 more element
A device comprising:
- a plurality of graphics processing units (GPU) each including a memory interface, wherein;
- a sub-set of the bit width of the communication links of the memory interface of a first GPU is connected to a corresponding sub-set of the bit width of the communication links of the memory interface of the second GPU;
- a sub-set of the bit width of the communication links of the memory interface of an Nth GPU is connected to a corresponding sub-set of the bit width of the communication links of the memory interface of an (N−1)th GPU;
- corresponding sub-sets of the bit width of the communication links of the memory interface of the second through (N−1)th GPU are connected to corresponding sub-sets of the bit width of the communication links of the memory interfaces of respective previous and next GPUs;
- and
- another sub-set of the bit width of the communication links of the memory interface of at least one of the plurality of GPUs is connected to a respective memory device, wherein the combined bit width of sub-sets of the communication links of the at least one of the plurality of GPUs is equal to the total bit width of the communication links of the memory interface of the at least one of the plurality of GPUs.
3 more elements
Dependencies are inferred from the claim text.