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US 10,095,890 B2Granted
Secure processor and a program for a secure processor
AssigneeSocionext Inc.
InventorsSeiji Goto, Jun Kamada, Taiji Tamiya
Life of this patent
Estimating the term…
Abstract
The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.
Claims20
A processor comprising:
- a translation look aside buffer including a plurality of table entries, each of the table entries including fields for a logical address, a physical address corresponding to the logical address, a context identifier identifying a context with which the logical address is associated, and a first flag indicating whether an address space associated with the context is secure;
- an execution circuit configured to execute execution codes corresponding to a plurality of contexts and to output a logical address associated with a current context among the plurality of contexts, the output logical address matching the logical address of a particular one of the plurality of table entries;
- a mode register configured to indicate whether the execution circuit is in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited;
- and
- a memory access control circuit configured to:
- receive the output logical address;
- determine whether the context identifier of the particular one of the table entries matches a reference context identifier of the current context and whether the first flag of the particular one of the plurality of table entries is set to a first state indicating that the address space associated with the context is secure;
- and
- when the execution circuit is in the first mode, the context identifier of the particular one of the plurality of table entries matches the reference context identifier, and the first flag of the particular one of the plurality of table entries is set to the first state, output the physical address of the particular one of the table entries by referring to the translation look aside buffer.
6 more elements
A processor comprising:
- a translation look aside buffer including a plurality of table entries, each of the table entries including fields for a logical address, a physical address corresponding to the logical address, a context identifier identifying a context with which the logical address is associated, and a first flag indicating whether an address space associated with the context is secure;
- an execution circuit configured to execute execution codes corresponding to a plurality of contexts and to output a logical address associated with a current context among the plurality of contexts, the output logical address matching the logical address of a particular one of the plurality of table entries;
- and
- a mode register configured to indicate whether the execution circuit is in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited;
- wherein, when the execution circuit is in the first mode, the context identifier of the particular one of the plurality of table entries matches a reference context identifier of the current context, and the first flag of the particular one of the plurality of table entries is set to a first state indicating that the address space associated with the context is secure, the physical address of the particular one of the table entries is output by referring to the translation look aside buffer.
2 more elements
Dependencies are inferred from the claim text.