Computer based system for verifying layout of semiconductor device and layout verify method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorChangho Han
Life of this patent
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Abstract
There is provided a method of verifying a Fin-based integrated circuit layout in a layout verifying system. The method includes receiving a layout corresponding to a specific integrated circuit unit, extracting one or more device codes from the layout, and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. Each device code is based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins of the layout.
Claims20
A method of operating a layout verifying system including a processor, the method comprising:
- receiving a circuit layout that corresponds to a circuit, the circuit layout including gate lines organized as gate line units;
- extracting device codes from the circuit layout using the processor,
- the device codes each being an expression of the gate lines in a same one of the gate line units in the circuit layout,
- the extracting the device codes from the circuit layout including assigning different values to the gate lines based on corresponding structures in the circuit layout that intersect the gate lines;
- and one of
- synthesizing a code stream from the device codes, and
- determining whether a target device code that corresponds to a target pattern is the same as one of the device codes by sequentially scanning the device codes for a match.
A method for detecting the same pattern as a target pattern in a specific integrated circuit unit in a layout design and verifying system including a processor, the method comprising:
- receiving a circuit layout that corresponds to a circuit, the circuit layout including gate lines organized as gate line units, wherein the receiving the circuit layout includes receiving a layout of the target pattern as the circuit layout;
- extracting device codes from the circuit layout using the processor, the device codes each being an expression of the gate lines in a same one of the gate line units in the circuit layout, the extracting the device codes from the circuit layout including assigning different values to the gate lines based on corresponding structures in the circuit layout that intersect the gate lines, wherein the extracting the device codes includes extracting a target device code from the layout of a target pattern, the target device code being based on an active region, the gate lines, and a number of intersecting points with silicon fins of the layout of the target pattern;
- and one of
- synthesizing a code stream from the device codes, and
- determining whether a target device code that corresponds to a target pattern is the same as one of the device codes by sequentially scanning the device codes for a match, wherein
- the one of synthesizing the code stream from the device codes and determining whether the target device code is the determining whether the target device that corresponds to the target pattern is the same as one of the device codes by sequentially scanning the device codes for the match, and
- the determining whether the target device that corresponds to the target pattern is the same as one of the device codes by sequentially scanning the device codes for the match is performed by determining whether a test code includes a same portion as the target device code by sequentially scanning the test code, the test code corresponding to the specific integrated circuit;
- and
- storing information about a location where the test code includes the same portion as the target device code in response to the same portion as the target device code being detected in the test code.
Dependencies are inferred from the claim text.