Systems and methods for symmetric H-tree construction with complicated routing blockages
AssigneeCadence Design Systems, Inc.
InventorsZhuo Li, Wen-Hao Liu, Charles Alpert, Brian Wilson
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AssigneeCadence Design Systems, Inc.
InventorsZhuo Li, Wen-Hao Liu, Charles Alpert, Brian Wilson
Estimating the term…
Disclosed herein are systems and methods to construct a symmetric clock-distribution H-tree in upper layers of an integrated circuit (IC), which may have complicated routing and/or placement blockages. The systems and methods disclosed herein may implement concomitant bottom-up wiring and top-down rewiring to achieve a clock-distribution tree symmetrically balanced across all of the hierarchical levels while respecting the complicated routing and/or placement blockages. Such symmetrically balanced clock-tree ensures that a clock-signal reaches all of the clock-sinks simultaneously or near simultaneously thereby minimizing clock-skew across the clock-sinks. The minimal skew symmetric clock-distribution H-tree may therefore be used for higher performance and high speed ICs.
A computer-implemented method comprising:
A system for circuit design, the system comprising:
Dependencies are inferred from the claim text.