Memory built-in self-test logic in an integrated circuit design
AssigneeCadence Design Systems, Inc.
InventorsNavneet Kaushik, Puneet Arora, Steven Lee Gregor, Norman Card
Life of this patent
Estimating the term…
Abstract
In one aspect, electronic design automation systems, methods, and non-transitory computer readable media are presented for adding a memory built-in self-test (MBIST) logic at register transfer level (RTL) or at netlist level into an integrated circuit (IC) design. In some embodiments, the MBIST logic is coupled to a physical memory module via a logical boundary of an intermediate level module that contains the physical memory module. The MBIST logic helps to keep intact integrity of the intermediate level module, making it more likely to meet any specified performance of the intermediate level module and reduce area overhead.
Claims20
A method comprising:
- causing a networking device to transmit instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- accessing, at a computing device, an integrated circuit design, the integrated circuit design having a tree structure hierarchy organizing a plurality of modules in the integrated circuit design;
- and
- adding, using one or more processors of the computing device, a memory built-in self test logic into the integrated circuit design,
- wherein the plurality of modules includes a root level module at a root level of the tree structure hierarchy, a plurality of leaf level modules including a first physical memory module at a first leaf level of the tree structure hierarchy, and an intermediate level module at an intermediate level of the tree structure hierarchy in between the root level and the first leaf level, and
- wherein the memory built-in self-test logic is coupled to the first physical memory module via a logical boundary of the intermediate level module that contains the first physical memory module.
A non-transitory computer-readable storage medium embodying instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
- accessing, at a computing device with the one or more processors, an integrated circuit design having a tree structure hierarchy organizing a plurality of modules in the integrated circuit design;
- adding, using the one or more processors of the computing device, a memory built-in self-test logic into the integrated circuit design,
- wherein the plurality of modules includes a root level module at a root level of the tree structure hierarchy, a plurality of leaf level modules including a first physical memory module at a first leaf level of the tree structure hierarchy, and an intermediate level module at an intermediate hierarchy level in between the root level and the first leaf level,
- wherein the memory built-in self-test logic is coupled to the first physical memory module via a logical boundary of the intermediate level module that contains the first physical memory module.
A computing device comprising:
- a memory;
- one or more hardware processors coupled to the memory;
- a processor-implemented design automation module configured to perform operations comprising:
- adding, using one or more hardware processors of the computing device, a memory built-in self-test logic at a register transfer level (RTL) into an integrated circuit design at the RTL and having a plurality of RTL modules,
- wherein the plurality of RTL modules includes a root level RTL module at a root hierarchy level, a plurality of leaf level RTL modules including a first physical memory module at a first leaf hierarchy level, and an intermediate level RTL module at an intermediate hierarchy level in between the root hierarchy level and the first leaf hierarchy level,
- wherein the memory built-in self-test logic is coupled to the first physical memory module via a logical boundary of the intermediate level RTL module that contains the first physical memory module.
Dependencies are inferred from the claim text.