Processor, accelerator, and direct memory access controller within a core reading/writing local synchronization flag area for parallel

A processor system comprising:

• at least one processor core including:
• a first memory;
• and
• components,
• wherein the first memory includes:
• an instruction area for storing, in advance, a task to be executed by each of the respective components;
• a synchronization flag area for storing a flag used to synchronize respective operations of the respective components therebetween;
• and
• a data area for storing data to be processed by the respective components and data processed by the respective components as processed data;
• and
• the respective components are configured to read an instruction included in tasks corresponding to the respective components stored in the instruction area when the processor system is booted, and operate in accordance with the instruction read by the respective components,
• wherein
• a first component of the respective components is configured to complete predetermined processing according to the instruction read, store data processed by the first component into the data area, and write a flag indicating completion of the predetermined processing into the synchronization flag area in accordance with tasks corresponding to the first component;
• and
• a second component other than the first component among the respective components is configured to start, even when a component other than the second component among the respective components is executing another processing, execution of an instruction read by the second component corresponding to a flag by reading the processed data stored in the data area in a case of confirming that the flag has been written by the instruction read by the second component, storing data subjected to the execution of the instruction into the data area after completion of the execution of the instruction, and writing a flag indicating the completion of the instruction into the synchronization flag area in accordance with tasks corresponding to the second component.