Accelerator architecture on a programmable platform
AssigneeAltera Corporation
InventorsDavid Shippy, Martin Langhammer, Jeffrey Eastlack
Life of this patent
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Abstract
An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
Claims27
An accelerated processor structure on a programmable integrated circuit device, the accelerated processor structure comprising:
- a processor;
- a plurality of configurable digital signal processors (DSPs), each configurable DSP comprising a circuit block, wherein the circuit block comprises a plurality of multipliers, wherein each configurable DSP is configured to use or bypass the plurality of multipliers by configuring at least one data connection between the plurality of multipliers;
- a first bus configured to transfer instructions from the processor to the configurable DSPs;
- a second bus configured to transfer processing data from the configurable DSPs to the processor;
- and
- data rotate circuitry coupled to the plurality of configurable DSPs and the second bus, wherein the data rotate circuitry is configured to align memory addresses of the processing data for the processing data to be accessed in aligned chunks.
A method of configuring an accelerated processor structure used for a programmable integrated circuit device, the method comprising:
- providing a processor;
- providing a plurality of configurable digital signal processors (DSPs), wherein at least one of the configurable DSPs includes:
- a circuit block, including,
- a plurality of multipliers,
- a first adder for adding multiplier outputs from the plurality of multipliers, and
- a second adder for adding data inputs to the circuit block to obtain an adder result, and outputting the adder result to at least one multiplier in the plurality of multipliers;
- configuring interconnections between the plurality of multipliers, the first adder and the second adder to selectively route data connections within the circuit block of at least one configurable DSP of the plurality of configurable DSPs;
- and
- configuring an arithmetic logic unit (ALU) that performs an arithmetic operation on the data inputs of the circuit block to generate an ALU output that is routed to one of the data inputs of the circuit block of the at least one configurable DSP.
A processor-readable non-transitory medium storing processor-executable instructions for configuring an accelerated processor structure used for a programmable integrated circuit device, the processor-executable instructions comprising:
- instructions executable by a processor to provide a plurality of configurable digital signal processors (DSPs), wherein at least one of the configurable DSPs includes:
- a circuit block, including,
- a plurality of multipliers,
- a first adder for adding multiplier outputs from the plurality of multipliers, and
- a second adder for adding data inputs to the circuit block to obtain an adder result, and outputting the adder result to at least one multiplier in the plurality of multipliers;
- instructions executable by the processor to configure interconnections between the plurality of multipliers, the first adder and the second adder to selectively route data connections within the circuit block of at least one configurable DSP of the plurality of configurable DSPs;
- and
- instructions executable by the processor to configure an arithmetic logic unit (ALU) that performs an arithmetic operation on the data inputs of the circuit block to generate an ALU output that is routed to one of the data inputs of the circuit block of the at least one configurable DSP.
Dependencies are inferred from the claim text.