Multi-processor startup system

A networking system, comprising:

• a bus;
• a first networking device processor that is coupled to a first networking device memory system and that includes a first networking device processor port that is connected to the bus;
• a second networking device processor that is coupled to a second networking device memory system and that includes a second networking device processor port that is connected to the bus and that is associated with at least one second networking device port register, wherein the second networking device processor is configured to:
• store networking device configuration information in the second networking device memory system;
• configure the at least one second networking device port register with an address mapping between the second networking device memory system and the first networking device memory system;
• and
• provide a write instruction to write the networking device configuration information to an address range included in the second networking device memory system, wherein the second networking device processor port converts the write instruction using the address mapping such that the networking device configuration information is written over the bus to the first networking device memory system.

A method for transferring configuration information, comprising:

• storing, by a primary processing system that is coupled to a secondary processing system by a bus that extends between a primary processing system port on the primary processing system and a secondary processing system port on the secondary processing system, configuration information in a primary memory system of the primary processing system;
• configuring, by the primary processing system, at least one primary port register for the primary processing system port with an address mapping between the primary memory system and a secondary memory system of the secondary processing system;
• and
• copying, by the primary processing system, the configuration information to the secondary memory system by providing a write instruction to write the configuration information to an address range included in the primary memory system, wherein the primary processing system port converts the write instruction using the address mapping such that the configuration information is written over the bus to the secondary memory system.