System address map for hashing within a chip and between chips
AssigneeArm Limited
InventorsPaul Gilbert Meyer, Gurunath Ramagiri
Life of this patent
Estimating the term…
Abstract
A system and method for accessing on-chip and off-chip memory in an integrated circuit data processing system. The system includes a number of nodes connected by an interconnect and also includes system address map logic in which a node register table is accessed using a hash function of the memory address to be accessed. A node identifier stored in a register of the node register table is an identifier of a remote-connection node when the memory address is in off-chip memory addresses and an identifier of a local-connection node when the memory address is in the off-chip memory. Transaction requests are routed using the node identifier selected using the hash function.
Claims16
An integrated circuit data processing system comprising:
- system address map logic comprising:
- a node register table comprising a plurality of registers that store node identifiers of a plurality of linked nodes of a network, the node identifiers comprising:
- an identifier of an on-chip remote-connection node in the integrated circuit that provides an interface to an external integrated circuit that, in turn, provides a home node for a first data resource associated with a first set of system memory addresses, and
- an identifier of an on-chip local-connection node in the integrated circuit that provides a home node for a second data resource associated with a second set of system memory addresses;
- hash address logic responsive to a memory address to provide a pointer to a register of the node register table;
- and
- a multiplexer, coupled to the node register table, that outputs a node identifier stored in the register of the node register table indicated by the pointer,
- where an identifier stored in a register of the node register table comprises:
- an identifier of the on-chip remote-connection node when the memory address is in the first set of system memory addresses;
- and
- an identifier of the on-chip local-connection node when the memory address is in the second set of system memory addresses.
A data processing system comprising:
- a first integrated circuit providing access to a first data resource;
- and
- a second integrated circuit providing access to a second data resource;
- the first integrated circuit further comprising:
- a request node having system memory map logic, the request node operable to generate a transaction request that utilizes a system address associated with the first or second data resource;
- a local-connection node that is a home node for the first data resource, where the local connection node is operable to receive the transaction request when the system address is associated with the first data resource and is further operable to communicate with the first data resource to service the data request;
- a remote-connection node operable to receive the transaction request when the system address is associated with the second data resource and further operable to communicate with the second integrated circuit to service the transaction request;
- and
- an interconnect circuit that couples between the request node and the remote-connection node and between the request node and the local-connection node,
- where system address map logic is responsive to the system address to produce a node identifier such that the transaction request is routed from the request node to the local-connection node when the system address is associated with the first data resource and the transaction request is routed from the request node to the remote-connection node when the system address is associated with the second data resource.
A method for accessing a data resource at a memory address in a data processing system comprising a first network of interconnected nodes in a first integrated circuit, first data resource accessible via a local-connection node in the first network and associated with a first set of system memory addresses, and second data resource accessible via the second integrated circuit and associated with a second set of system memory addresses, the first and second networks coupled via a remote-connection node of the first network, the method comprising, in the first integrated circuit:
- generating, by a first request node of the first network, a transaction request comprising a system address and an identifier of the first request node;
- producing, by hash address logic of the first integrated circuit, a pointer to a register of a first register table of node identifiers, the pointer being a first hash function of the system address;
- selecting, by a multiplexer, a target node identifier in the register of the first register table;
- and
- routing the transaction request through the first network to a first target node corresponding to the target node identifier;
- where the target node identifier stored in a register of the first node register table comprises:
- an identifier of the local-connection node of the first network when the memory address is in the first set of system memory addresses;
- and
- an identifier of the remote-connection node of the first network when the memory address is in the second set of system memory addresses.
A method for accessing a data resource at system address in a data processing system comprising a network of interconnected nodes, the method comprising:
- selecting, from a system address, an identifier of a first home node of the network from a plurality of stored identifiers using hash function logic;
- generating, by a first request node of the network, a transaction request comprising the system address, an identifier of the first request node and a first transaction identifier;
- routing the transaction request to the first home node using the identifier of the first home node;
- storing the transaction request identifier and the identifier of the first request node of the transaction request;
- and
- when a transaction identifier of a received response to a transaction request matches the stored transaction request identifier, routing the received response to the first request node.
Dependencies are inferred from the claim text.