Multibit NAND media using pseudo-SLC caching technique
AssigneeToshiba Memory Corporation
InventorsNarasimhulu Dharani Kotte, Senthil Thamgaraj, Robert Reed, Hitoshi Kondo
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Abstract
A solid state drive (SSD) with pseudo-single-level cell (pSLC) caching and a method of caching data in an SSD is disclosed. In one embodiment, the SSD includes a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to a memory controller. A first portion of the plurality of multibit NAND media devices is configured to operate as a pSLC cache and a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area. In one embodiment, the pSLC cache comprises a first area for a pSLC write cache and a second area for a pSLC read cache.
Claims20
A solid state drive (SSD) comprising:
- a memory controller;
- a plurality of multibit NAND media devices arranged in one or more channels communicatively coupled to the memory controller;
- one or more volatile memory devices communicatively coupled to the memory controller;
- and
- a host interface communicatively coupled to the memory controller, wherein
- a first portion of the plurality of multibit NAND media devices is configured to operate as a pseudo-single-level cell (pSLC) cache,
- a second portion of the plurality of multibit NAND media devices is configured to operate as a multibit NAND media storage area, and
- the memory controller is configured to:
- write data received via the host interface to one or more blocks of the pSLC cache,
- transfer data from the one or more blocks of the pSLC cache to one or more blocks of the multibit NAND media storage area,
- read the data transferred to the multibit NAND media storage area and determine if an error correction code (ECC) error correction threshold has been exceeded for the data read, and
- when the data read has been determined to exceed the ECC error correction threshold, write such data to the pSLC cache.
A method of caching data in an solid state drive (SSD) having a plurality of multibit NAND media devices, the method comprising:
- configuring a first portion of the plurality of multibit NAND media devices to operate as a pseudo-single-level cell (pSLC) cache;
- configuring a second portion of the plurality of multibit NAND media devices to operate as a multibit NAND storage area;
- receiving data from a host device connected to the SSD;
- writing the data to one or more blocks of the pSLC cache;
- transferring data from the one or more blocks of the pSLC cache to one or more blocks of the multibit NAND media storage area;
- reading the data transferred to the multibit NAND media storage area;
- determining if an error correction code (ECC) error correction threshold has been exceeded for the data read;
- and
- for the data read exceeding the ECC error correction threshold, writing such data to the pSLC cache.
Dependencies are inferred from the claim text.