Computer system including synchronous input/output and hardware assisted purge of address translation cache entries of synchronous input/output transactions

A synchronous input/output (I/O) computing system comprising a processor and a memory unit that stores program instructions, the system configured to purge one or more address translation entries in response to the processor executing the program instructions to perform:

• issuing, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction;
• selecting a device table entry from a device table, loading the entry into a device table cache (DTC), requesting required address translation entries, installing the required address translation entries in the address translation cache and transferring data packets corresponding to the transaction using the selected device table entry and the required address translation entries;
• and
• automatically purging the address translation cache entries associated the a transaction in response to detecting that the transaction is completed, further comprising identifying at least one stale address translation cache entry in response to detecting that the transaction is completed, and automatically purging, via a host bridge, the at least one stale address translation cache entry from an address translation cache without receiving a purge command from firmware.

A computer program product, the computer program product comprising a non-transitory computer readable storage medium having program instructions for purging a device table cache (DTC) included in a synchronous input/output (I/O) computing system, the program instructions executable by a processor to perform:

• issuing, via an operating system running on the synchronous I/O computing system, a synchronous I/O command indicating a request to perform a transaction;
• selecting a device table entry from a device table, loading the entry into the DTC, requesting required address translation entries, installing the required address translation entries in the address translation cache and transferring data packets corresponding to the transaction using the selected device table entry and the required address translation entries;
• and
• automatically purging the address translation cache entries associated with the transaction in response to detecting that the transaction is completed, further comprising identifying at least one stale address translation cache entry in response to detecting that the transaction is completed, and automatically purging, via a host bridge, the at least one stale address translation cache entry from an address translation cache without receiving a purge command from firmware.