Memory device with flexible data transfer rate interface and method thereof
AssigneeMacronix International Co., Ltd.
InventorsKuen-Long Chang, Su-Chuch Lo, Chao Hsin Lin, Ken-Hui Chen
Life of this patent
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Abstract
A memory device includes an input/output interface configured to receive and output signals. The input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at a rising or falling edge of a clock cycle. The data sequence information specifies an input or output data sequence.
Claims20
A memory device comprising:
- an input/output interface configured to receive input and output signals, wherein:
- the input/output interface is configured to receive a memory address to be accessed and data sequence information within a clock cycle or at an edge of a clock cycle, the data sequence information specifying an input or output data sequence;
- and
- the data sequence information specifies a byte sequence, the byte sequence determining whether high bytes are input or output at rising edges or at falling edges of the clock cycle.
A method of transferring data, the method comprising:
- forwarding to a memory device a memory address to be accessed and data sequence information within a clock cycle or at an edge of a clock cycle, the data sequence information specifying an input or output data sequence,
- wherein the data sequence information specifies a byte sequence, the byte sequence determining whether high bytes are input or output at rising edges or at falling edges of the clock cycle.
A non-transitory computer-readable storage medium storing instructions which, when executed by one or more processors, cause the one or more processors to:
- forward to a memory device a memory address to be accessed and data sequence information within a clock cycle or at an edge of a clock cycle, the data sequence information specifying an input or output data sequence,
- wherein the data sequence information specifies a byte sequence, the byte sequence determining whether high bytes are input or output at rising edges or at falling edges of the clock cycle.
Dependencies are inferred from the claim text.