Test circuit for 3D semiconductor device and method for testing thereof
AssigneeIndustry-Academic Cooperation Foundation, Yonsei University
InventorsSung Ho Kang, In Geol Lee
Life of this patent
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Abstract
Disclosed herein is a test circuit for a 3D semiconductor device for detecting soft errors and a method for testing thereof. The test circuit includes a first Multiple Input Signature Register (MISR) disposed in a first semiconductor chip, the first MISR compressing a first test result signal corresponding to a test pattern, a second MISR disposed in a second semiconductor chip stacked on or under the first semiconductor chip, the second MISR compressing a second test result signal corresponding to the test pattern, and a first error detector to detect a soft error by comparing a first output signal output from the first MISR with a second output signal output from the second MISR.
Claims10
A test circuit for a 3-dimensional (3D) semiconductor device, the test circuit comprising:
- a first linear feedback shift register (LFSR) disposed in a first semiconductor chip to generate a first test pattern and provide the first test pattern to a plurality of scan chains disposed in the first semiconductor chip;
- a first Multiple Input Signature Register (MISR) disposed in the first semiconductor chip to receive a first test signal corresponding to the first test pattern and output from the plurality of scan chains disposed in the first semiconductor chip, compress the first test signal and output a first output signal corresponding to the compressed first test signal;
- a second linear feedback shift register (LFSR) disposed in a second semiconductor chip stacked on or under the first semiconductor chip to generate a second test pattern and provide the second test pattern to a plurality of scan chains disposed in the second semiconductor chip, the first test pattern and the second test pattern being the same with each other;
- a second MISR disposed in the second semiconductor chip stacked on or under the first semiconductor chip to receive a second test signal corresponding to the second test pattern and output from the plurality of scan chains disposed in the second semiconductor chip, compress the second test signal and output a second output signal corresponding to the compressed second test signal;
- and
- a first error detector to detect a soft error of the first and second semiconductor chips by comparing the first output signal output from the first MISR and passing through a Through Silicon Via (TSV) disposed between the first semiconductor chip and the second semiconductor chip with the second output signal output from the second MISR.
A method for testing of a 3-dimensional (3D) semiconductor device, comprising:
- generating, by a first linear feedback shift register (LFSR) disposed in a first semiconductor chip, a first test pattern and providing, by the first LFSR, the first test pattern to a plurality of scan chains disposed in the first semiconductor chip;
- receiving, by a first Multiple Input Signature Register (MISR) disposed in the first semiconductor chip, a first test signal corresponding to the first test pattern and output from the plurality of scan chains disposed in the first semiconductor chip, compressing, by the first MISR, the first test signal corresponding to the first test pattern and outputting, by the first MISR, a first output signal corresponding to the compressed first test signal;
- generating, by a second linear feedback shift register (LFSR) disposed in a second semiconductor chip stacked on or under the first semiconductor chip, a second test pattern and providing, by the second LFSR, the second test pattern to a plurality of scan chains disposed in the second semiconductor chip;
- receiving, by a second Multiple Input Signature Register (MISR) disposed in the second semiconductor chip, a second test signal corresponding to the second test pattern and output from the plurality of scan chains disposed in the second semiconductor chip, compressing, by the second MISR, a second test signal corresponding to the second test pattern and outputting, by the second MISR, a second output signal corresponding to the compressed second test signal, the first test pattern and the second test pattern being the same with each other;
- and
- detecting a soft error of the first and second semiconductor chips by comparing the first output signal output from the first MISR and passing through a Through Silicon Via (TSV) disposed between the first semiconductor chip and the second semiconductor chip with the second output signal output from the second MISR.
Dependencies are inferred from the claim text.