US 10,095,568 B2 · Background reads to condition programmed semiconductor memory cells

Abstract

Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

Claims20

Dependent claims

An apparatus comprising:

a semiconductor memory comprising memory cells arranged into addressable blocks, each of the memory cells characterized as a non-volatile memory cell and configured to store multiple bits;
and
a program/read control circuit configured to program data sets to and read data sets from the memory cells in the addressable blocks to service a sequence of host access commands, and to perform background reads in conjunction with the servicing of the host access commands, the background reads reading a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration to condition the memory cells prior to a first read operation associated with the host access commands,
the program/read control circuit configured to further perform the first read operations from the conditioned memory cells to service respective host access commands after the respective background reads.

1 more element

A method comprising:

servicing a plurality of host access commands to transfer data between a host device and a semiconductor memory, the semiconductor memory comprising memory cells arranged into addressable blocks, each of the memory cells characterized as a non-volatile memory cell and configured to store multiple bits;
performing a plurality of background reads during the servicing step, the background reads reading a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration to condition the memory cells prior to a first read operation associated with the host access commands;
and
performing the first read operations from the conditioned memory cells to service respective host access commands after the respective background reads.

1 more element

Dependencies are inferred from the claim text.

Background reads to condition programmed semiconductor memory cells

Life of this patent

Background reads to condition programmed semiconductor memory cells

Life of this patent

Abstract

Claims20