Memory controller with error detection and retry modes of operation

A method of operation in a memory controller, the method comprising:

• transmitting a write command and a first error detection code to a memory device using a first transmitter;
• transmitting write data and a second error detection code to a memory device using a plurality of second transmitters, the second error detection code encoded by the controller using the write data, the write data being transmitted in accordance with one of a plurality of modes, a first mode including data comprising symbols respectively transferred on rising and falling edges per clock cycle of a clock signal, and a second mode including data transferred with one symbol per clock cycle;
• and
• using circuitry to re-transmit the write data to the memory device in the event that the memory device detects an error condition dependent on at least one error in the write data as received by the memory device and to re-transmit the write command to the memory device in the event of error that the memory device detects error in the write command;
• wherein
• the memory controller is to re-transmit the write data to the memory device in the event of the error condition,
• the memory controller is to re-transmit the write command to the memory device in the event of error that the memory device detects error in the write command, and
• an indication of at least one of the error condition or error in the write command is to be received by the memory controller from the memory device via a link not used to transmit the write data to the memory device.

A memory controller for an electrically erasable programmable memory device, the memory controller comprising:

• means for transmitting a write command and a first error detection code to a memory device;
• means for transmitting write data and a second error detection code to the memory device, the second error detection code encoded by the controller in connection with the write data, wherein the means for transmitting the write data and the second error detection code is operable to transmit the write data in accordance with one of a plurality of modes, a first mode including data comprising symbols respectively transferred on rising and falling edges per clock cycle of a clock signal, and a second mode including data symbols respectively transferred with one symbol per clock cycle;
• means for re-transmitting the write data to the memory device in the event that the memory device detects an error condition dependent on at least one error in the write data as received by the memory device and re-transmitting the write command to the memory device in the event of error that the memory device detects error in the write command;
• and
• wherein
• the memory controller is to retransmit the write data to the memory device in the event that the means for identifying that the transmitted write data as received by the memory device reflects the error condition,
• the memory controller to re-transmit the write command to the memory device in the event of error that the memory device detects error in the write command, and
• an indication of at least one of the error condition or error in the write command is to be received by the memory controller from the memory device via a link not used to transmit the write data to the memory device.