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US 10,095,543 B1Granted
Computing in parallel processing environments
AssigneeMellanox Technologies, Ltd.
InventorsPatrick Robert Griffin, Mathew Hostetter, Anant Agarwal, Chyi-Chang Miao
Life of this patent
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Abstract
A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
Claims32
A multicore computing system, comprising:
- a plurality of cores, with multiple ones of the plurality of cores each comprising
- a processor;
- and
- switching circuitry configured to couple the processor to a network among the cores for transferring memory access requests and responses between cores and memory coupled to the multicore computing system;
- with a first one of the plurality of cores configured to send an inter-processor interrupt request to a target core of the plurality of cores over the network, by being configured to:
- perform a store operation to a page in memory, which page is marked as a memory mapped I/O page, with the memory mapped I/O page having an entry that indicates a network location of an interrupt reflector circuitry that is coupled to the network;
- and with the system further comprising:
- the interrupt reflector circuitry configured to:
- receive the inter-processor interrupt request over the network from the first processor on the first one of the plurality of cores,
- determine from the inter-processor interrupt request, the target core of the inter-processor interrupt request, and
- forward the inter-processor interrupt request message to the determined target core of the plurality of cores.
8 more elements
A multicore computing system comprises:
- interrupt reflector circuitry;
- a multicore processor device comprising a plurality of cores, with multiple ones of the plurality of cores each comprising:
- a processor;
- and
- switching circuitry configured to couple the processor to a network among the cores, the network for transferring memory access requests and responses from memory between cores and memory coupled to the multicore computing system;
- with a first one of the plurality of cores configured to send an inter-processor interrupt request to a target core of the plurality of cores, over the network by being configured to:
- perform a store operation to a page in memory, which page is marked as a memory mapped I/O page, with the memory mapped I/O page having an entry that indicates a network location of the interrupt reflector circuitry that is coupled to the network;
- the interrupt reflector circuitry configured to:
- receive the inter-processor interrupt request over the network from the configured core;
- determine from the received inter-processor interrupt request a core that is the targeted core of the interrupt request, and
- forward the inter-processor interrupt request to the targeted core, which causes an interrupt at the targeted core.
8 more elements
A multicore computing system comprises:
- interrupt reflector circuitry;
- a multicore processor device comprising a plurality of cores, with multiple ones of the plurality of cores each comprising:
- a processor;
- and
- switching circuitry configured to couple the processor to a network among the cores, the network for transferring memory access requests and responses from memory between cores and memory coupled to the multicore computing system;
- and
- a first core of the plurality of cores, configured to:
- store an address of a given memory location;
- instruct a cache controller on the first core to notify the first core when the given memory location is written into or read from or is a target of an atomic operation or incremented or modified by checking addresses in remotely requested memory operations serviced by the cache controller against the address of the given memory location, and when the address of the given memory location and addresses of one or more of the remotely requested memory operations match, then the processor on the first core is interrupted, with the first core further configured to:
- send an inter-processor interrupt request to a target core of the plurality of cores, over the network, with the first one of the plurality of cores being configured to:
- perform a store operation to a page in memory, which page is marked as a memory mapped I/O page, with the memory mapped I/O page having an entry that indicates a network location of the interrupt reflector circuitry that is coupled to the network, and with the interrupt reflector circuitry configured to:
- receive the interrupt request over the network from the configured core;
- determine from the received interrupt request a core that is the targeted core of the interrupt request, and
- send a message to the determined targeted core of the plurality of cores, which message includes information that causes an interrupt at the targeted one of the plurality of cores.
11 more elements
A method on a multicore computing system comprising a plurality of cores, each comprising a processor;
- and switching circuitry configured to couple the processor to a network among the plurality of cores for transferring memory access requests and responses between the plurality of cores and memory coupled to the multicore computing system, the method comprising:
- sending by a core of the cores, an inter-processor interrupt request to inter-processor interrupt reflector circuity by:
- performing a store operation to a page in memory, which page is marked as memory-mapped I/O page having a page table entry that indicates the network location of the inter-processor interrupt reflector circuit;
- receiving by the inter-processor interrupt reflector circuit the inter-processor interrupt request;
- determining by the inter-processor interrupt reflector circuit from the inter-processor interrupt request, a targeted core of the interrupt request;
- and
- sending by the inter-processor interrupt reflector circuity a message to the determined targeted core of the plurality of cores, which message includes information that causes an interrupt at the targeted one of the plurality of cores.
4 more elements
Dependencies are inferred from the claim text.