US 10,095,523 B2Granted

Hardware counters to track utilization in a multithreading computer system

AssigneeInternational Business Machines Corporation

InventorsJane H. Bartik, Jonathan D. Bradbury, Gary M. King, Daniel V. Rosa, Donald W. Schmidt

Life of this patent

Estimating the term…

Loading patent…

Abstract

Embodiments relate tracking utilization in a multithreading (MT) computer system. According to one aspect, a computer system includes a configuration with a core configured to operate in a MT that supports multiple threads on shared resources of the core. The core is configured to perform a method that includes resetting a plurality of utilization counters. The utilization counters include a plurality of sets of counters. During each clock cycle on the core, a set of counters is selected from the plurality of sets of counters. The selecting is based on a number of currently active threads on the core. In addition, during each clock cycle a counter in the selected set of counters is incremented based on an aggregation of one or more execution events at the multiple threads of the core. Values of the utilization counters are provided to a software program.

Claims7

Dependent claims

A computer implemented method for tracking utilization in a configuration comprising a core configured to operate in a multithreading (MT) mode, the MT mode supporting multiple threads on shared resources of the core, the method comprising:

resetting a plurality of utilization counters, the utilization counters comprising a plurality of sets of counters including a first set of counters and a second set of counters, each set of counters corresponding to a different number of currently active threads and each set of counters non-overlapping with each other set of counters;
performing for each clock cycle on the core:
selecting a set of counters from the plurality of sets of counters, the selecting based on a number of currently active threads on the core and not based on which specific threads of the multiple threads are currently active, wherein the first set of counters is selected based on exactly one of the multiple threads being currently active, and the second set of counters is selected based on exactly two of the multiple threads being currently active;
and
incrementing a counter in the selected set of counters, the incrementing based on an aggregation of one or more execution events at the multiple threads of the core;
and
providing values of the utilization counters to a software program.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/824,123Filed 12 Aug 2015 · continuation
Priority: 27 Mar 2014
Published: US 2015/0277922 A13 Dec 2015
Granted: 9 Oct 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/3861
Concurrent instruction execution, e.g. pipeline or look ahead: recovery, e.g. branch miss-prediction, exception handling

Family

Application14/226,980Parent of this continuation · filed 27 Mar 2014
US 2015/0347150 A1Pre-grant publication · published 3 Dec 2015
US 10,102,004 B2Related patent
US 2015/0277922 A1Published application
US 10,095,523 B2This patent

From the US filing history. Foreign family members aren’t listed.