Apparatus and method for low-latency invocation of accelerators

A processor comprising:

• execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands, the accelerator invocation instruction to store command data specifying one or more commands, the command data to be read by one or more accelerators;
• the command data to be read by one or more accelerators which are to responsively attempt to execute the one or more commands identified by the command data;
• and
• an accelerator context save/restore pointer to identify a region within system memory where one of the one or more accelerators is to save the accelerator's state upon a switch from a first context to a second context and to later restore its state upon returning to the first context, wherein entries in a translation lookaside buffer (TLB) associated with the accelerator are locked prior to saving the accelerator's state and unlocked after the saving.