Interrupt return instruction with embedded interrupt service functionality
AssigneeIntel Corporation
InventorsZhen Fang, Xiaowei Jiang, Srihari Makineni, Rameshkumar G. Illikkal, Ravishankar Iyer
Life of this patent
Estimating the term…
Abstract
An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
Claims25
A processor comprising:
- a decoder to decode a single instruction into a decoded, single instruction;
- and
- an execution unit to execute the decoded, single instruction to:
- perform an operation on an input parameter of the single instruction, and
- return program control to an invoking program that was interrupted, wherein an instruction set supported by the processor does not include a separate instruction to perform the operation, and the operation is an insert operation to insert virtual and physical addresses into a translation look-aside buffer.
A method comprising:
- decoding a single instruction with a decoder of a processor into a decoded, single instruction;
- and
- executing the decoded, single instruction with an execution unit of the processor to:
- perform an operation on an input parameter of the single instruction, and
- return program control to an invoking program that was interrupted, wherein an instruction set supported by the processor does not include a separate instruction to perform the operation, and:
- the operation is an insert operation inserting virtual and physical addresses into a translation look-aside buffer,
- the operation is passing input parameters to an accelerator of the processor, or
- a same opcode of the single instruction, when executed on a second processor, is to return program control to an invoking program that was interrupted but is not to perform an operation on an input parameter of the single instruction.
A processor comprising:
- a decoder to decode a single instruction into a decoded, single instruction;
- and
- an execution unit to execute the decoded, single instruction to:
- perform an operation on an input parameter of the single instruction, and
- return program control to an invoking program that was interrupted, wherein an instruction set supported by the processor does not include a separate instruction to perform the operation, and the operation is to pass input parameters to an accelerator of the processor.
A processor comprising:
- a decoder to decode a single instruction into a decoded, single instruction;
- and
- an execution unit to execute the decoded, single instruction to:
- perform an operation on an input parameter of the single instruction, and
- return program control to an invoking program that was interrupted, wherein an instruction set supported by the processor does not include a separate instruction to perform the operation, and a same opcode of the single instruction, when executed on a second processor, is to return program control to an invoking program that was interrupted but is not to perform an operation on an input parameter of the single instruction.
Dependencies are inferred from the claim text.