Instruction block address register
AssigneeMicrosoft Technology Licensing, LLC
InventorsDouglas C. Burger, Aaron L. Smith
Life of this patent
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Abstract
Apparatus and methods are disclosed for controlling instruction flow in block-based processor architectures. In one example of the disclosed technology, an instruction block address register stores an index address to a memory storing a plurality of instructions for an instruction block, the indexed address being inaccessible when the processor is in one or more unprivileged operational modes, one or more execution units configured to execute instructions for the instruction block, and a control unit configured to fetch and decode two or more of the plurality of instructions from the memory based on the indexed address.
Claims22
A block-based processor comprising:
- a control unit comprising at least one instruction block address register that indexes an entry location in a memory for fetching an instruction block, the instruction block address register being implicitly written by executing a branch instruction with one of the execution units, the instruction block address register being not visible from one or more operating modes of the block-based processor;
- and
- at least one processor core having a plurality of execution units and being configured to fetch and execute a first instruction of the instruction block from the memory at a location indexed by the instruction block address register and an incremental offset.
An apparatus comprising memory coupled to a block-based processor, the apparatus comprising:
- an instruction block address register storing an index address to the memory storing a plurality of instructions for an instruction block, the index address being inaccessible when the processor is in one or more unprivileged operational modes;
- one or more execution units configured to execute instructions for the instruction block;
- and
- a control unit configured to fetch and decode two or more of the plurality of instructions from the memory based on the indexed address and an incremental offset.
A method of operating a block-based processor, the method comprising:
- reading a memory address stored in an instruction block address register, the memory address indicating an entry point for an instruction block, the memory address and the instruction block address register being not accessible to a currently executing process or thread of the block-based processor comprising the instruction block;
- and
- fetching and decoding at least two instructions of the instruction block indicated by the memory address by adding an incremental offset to the memory address.
Dependencies are inferred from the claim text.