Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure

A system comprising:

• one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
• instantiating, within an application software development environment, an input array, an output array, and a plurality of virtual processor instances, wherein the input array stores input image data of one or more line groups of an image, and wherein the output array stores output image data of one or more line groups of the image, wherein each virtual processor instance comprises one or more registers, each virtual processor instance being configured to execute instructions of an instruction set architecture having a load instruction that references locations within the input array of the application software development environment, and wherein each virtual processor instance is configured to execute a respective thread of a plurality of threads, wherein each thread is assigned to a respective line group position within a line group of the image;
• receiving a load instruction of the instruction set architecture of the virtual processor instances, wherein the load instruction identifies a target register and specifies a load address having a source x offset and a source y offset, the source x offset and the source y offset being offsets relative to a line group position to which a thread executed by a virtual processor instance is assigned;
• executing a respective thread having the load instruction by each virtual processor instance of the plurality of virtual processor instances thereby simulating operations of an image processor having a two-dimensional shift register array and a two-dimensional array of processing elements, wherein executing the load instruction includes:
• obtaining a line group position to which a thread executed by the virtual processor instance is assigned,
• computing a two-dimensional source position in the line group of the image including using the source x offset and the source y offset of the load address as offsets relative to the line group position to which the thread executed by the virtual processor instance is assigned, and
• copying, to a target register of the virtual processor instance identified by the load instruction, data from a location in the input image array corresponding to the computed two-dimensional source position in the line group of the image.

A computer-implemented method comprising:

• instantiating, within an application software development environment, an input array, an output array, and a plurality of virtual processor instances, wherein the input array stores input image data of one or more line groups of an image, and wherein the output array stores output image data of one or more line groups of the image, wherein each virtual processor instance comprises one or more registers, each virtual processor instance being configured to execute instructions of an instruction set architecture having a load instruction that references locations within the input array of the application software development environment, and wherein each virtual processor instance is configured to execute a respective thread of a plurality of threads, wherein each thread is assigned to a respective line group position within a line group of the image;
• receiving a load instruction of the instruction set architecture of the virtual processor instances, wherein the load instruction identifies a target register and specifies a load address having a source x offset and a source y offset, the source x offset and the source y offset being offsets relative to a line group position to which a thread executed by a virtual processor instance is assigned;
• executing a respective thread having the load instruction by each virtual processor instance of the plurality of virtual processor instances thereby simulating operations of an image processor having a two-dimensional shift register array and a two-dimensional array of processing elements, wherein executing the load instruction includes:
• obtaining a line group position to which a thread executed by the virtual processor instance is assigned,
• computing a two-dimensional source position in the line group of the image including using the source x offset and the source y offset of the load address as offsets relative to the line group position to which the thread executed by the virtual processor instance is assigned, and
• copying, to a target register of the virtual processor instance identified by the load instruction, data from a location in the input image array corresponding to the computed two-dimensional source position in the line group of the image.

One or more non-transitory computer storage media encoded with program code that when processed by a computing system causes the computing system to perform operations comprising:

• instantiating, within an application software development environment, an input array, an output array, and a plurality of virtual processor instances, wherein the input array stores input image data of one or more line groups of an image, and wherein the output array stores output image data of one or more line groups of the image, wherein each virtual processor instance comprises one or more registers, each virtual processor instance being configured to execute instructions of an instruction set architecture having a store instruction that references locations within the output array of the application software development environment, and wherein each virtual processor instance is configured to execute a respective thread of a plurality of threads, wherein each thread is assigned to a respective line group position within a line group of the image;
• receiving a store instruction of the instruction set architecture of the virtual processor instances, wherein the store instruction identifies a source register and specifies a store address, the store address having a target x offset and a target y offset, the target x offset and the target y offset being offsets relative to a line group position to which a thread executed by a virtual processor instance is assigned;
• and
• executing a respective thread having the store instruction by each virtual processor instance of the plurality of processor instances thereby simulating operations of an image processor having a two-dimensional shift register array and a two-dimensional array of processing elements, wherein executing the store instruction includes:
• obtaining a line group position to which a thread executed by the virtual processor instance is assigned,
• computing a two-dimensional target position in the line group of the image including using the target x offset and the target y offset of the store address as offsets relative to the line group position to which the thread executed by the virtual processor instance is assigned, and
• copying, to a location in the output image array corresponding to the computed two-dimensional target position in the line group of the image, data from a source register of the virtual processor instance identified by the store instruction.

A system comprising:

• one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
• instantiating, within an application software development environment, an input array, an output array, and a plurality of virtual processor instances, wherein the input array stores input image data of one or more line groups of an image, and wherein the output array stores output image data of one or more line groups of the image, wherein each virtual processor instance comprises one or more registers, each virtual processor instance being configured to execute instructions of an instruction set architecture having a store instruction that references locations within the output array of the application software development environment, and wherein each virtual processor instance is configured to execute a respective thread of a plurality of threads, wherein each thread is assigned to a respective line group position within a line group of the image;
• receiving a store instruction of the instruction set architecture of the virtual processor instances, wherein the store instruction identifies a source register and specifies a store address, the store address having a target x offset and a target y offset, the target x offset and the target y offset being offsets relative to a line group position to which a thread executed by a virtual processor instance is assigned;
• and
• executing a respective thread having the store instruction by each virtual processor instance of the plurality of virtual processor instances thereby simulating operations of an image processor having a two-dimensional shift register array and a two-dimensional array of processing elements, wherein executing the store instruction includes:
• obtaining a line group position to which a thread executed by the virtual processor instance is assigned,
• computing a two-dimensional target position in the line group of the image including using the target x offset and the target y offset of the store address as offsets relative to the line group position to which the thread executed by the virtual processor instance is assigned, and
• copying, to a location in the output image array corresponding to the computed two-dimensional target position in the line group of the image, data from a source register of the virtual processor instance identified by the store instruction.

A computer-implemented method comprising:

• instantiating, within an application software development environment, an input array, an output array, and a plurality of virtual processor instances, wherein the input array stores input image data of one or more line groups of an image, and wherein the output array stores output image data of one or more line groups of the image, wherein each virtual processor instance comprises one or more registers, each virtual processor instance being configured to execute instructions of an instruction set architecture having a store instruction that references locations within the output array of the application software development environment, and wherein each virtual processor instance is configured to execute a respective thread of a plurality of threads, wherein each thread is assigned to a respective line group position within a line group of the image;
• receiving a store instruction of the instruction set architecture of the virtual processor instances, wherein the store instruction identifies a source register and specifies a store address, the store address having a target x offset and a target y offset, the target x offset and the target y offset being offsets relative to a line group position to which a thread executed by a virtual processor instance is assigned;
• and
• executing a respective thread having the store instruction by each virtual processor instance of the plurality of virtual processor instances thereby simulating operations of an image processor having a two-dimensional shift register array and a two-dimensional array of processing elements, wherein executing the store instruction includes:
• obtaining a line group position to which a thread executed by the virtual processor instance is assigned,
• computing a two-dimensional target position in the line group of the image including using the target x offset and the target y offset of the store address as offsets relative to the line group position to which the thread executed by the virtual processor instance is assigned, and
• copying, to a location in the output image array corresponding to the computed two-dimensional target position in the line group of the image, data from a source register of the virtual processor instance identified by the store instruction.