Systems and methods for offloading processing from a host to storage processing units using an interconnect network
AssigneeWestern Digital Technologies, Inc.
InventorsArup De, Kiran Kumar Gunnam
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Abstract
Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such system includes a host having a processing task, a plurality of storage processing units (SPUs), a host interface configured to enable communications between the host and each of the plurality of SPUs, and an interconnection network coupled to at least two of the plurality of SPUs, where the host is configured to command at least one of the plurality of SPUs to perform the processing task, and command the interconnection network to couple two or more of the plurality of SPUs.
Claims17
A system for offloading processing from a host to one or more storage processing units each comprising a non-volatile memory (NVM), the system comprising:
- a host having a processing task;
- a plurality of storage processing units (SPUs);
- a host interface configured to enable communications between the host and each of the plurality of SPUs;
- and
- an interconnection network coupled to at least three of the plurality of SPUs;
- wherein the host is configured to:
- command at least one of the plurality of SPUs to perform the processing task;
- and
- command the interconnection network to couple three or more of the plurality of SPUs, wherein the interconnection network enables any one of the coupled three or more of the plurality of SPUs to communicate with any other one of the coupled three or more of the plurality of SPUs, and wherein each of the plurality of SPUs comprises an NVM and a processing circuitry configured to perform the processing task.
A method for offloading processing from a host to one or more storage processing units each comprising a non-volatile memory (NVM), the method comprising:
- sending a processing task from the host to a first storage processing unit (SPU) of a plurality of SPUs via a host interface;
- commanding the first SPU to perform the processing task;
- and
- commanding an interconnection network to couple three or more of the plurality of SPUs, wherein the interconnection network enables any one of the coupled three or more of the plurality of SPUs to transfer data directly to any other one of the coupled three or more of the plurality of SPUs, and wherein each of the plurality of SPUs comprises an NVM and a processing circuitry configured to perform the processing task.
Dependencies are inferred from the claim text.