Memory access control
AssigneeIntel Corporation
InventorsRezaul Haque, Lady Nataly Pinilla Pico
Life of this patent
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Abstract
The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.
Claims22
An apparatus comprising:
- partition control circuitry to control at least one partition of a memory array, the partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to provide an active/idle signal having an active state during execution of the legitimate memory access command or having an idle state in response to completion of execution of the legitimate memory access command.
A method comprising:
- receiving, by a memory controller, an active/idle signal from partition control circuitry;
- wherein the partition control circuitry to control at least one partition of a memory array and wherein the active/idle signal has a state indicative of one of an active state or an idle state of the partition control circuitry;
- receiving, by the memory controller, a memory access command;
- determining, by the memory controller, if the memory access command is legitimate;
- and
- enabling, by the memory controller for the partition control circuitry, a clock signal if the memory access command is legitimate and if the active/idle signal is in an idle state.
A system comprising:
- memory controller circuitry to receive a memory access command and determine if the memory access command is legitimate or illegitimate, and to enable a clock signal if the memory access command is legitimate;
- and
- partition control circuitry to control at least one partition of a memory array, the partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to provide an active/idle signal having an active state during execution of the legitimate memory access command or having an idle state in response to completion of execution of the legitimate memory access command;
- wherein the memory controller circuitry to disable the clock signal to the partition control circuitry when the active/idle signal is in an idle state.
A computer-readable storage device having stored thereon instructions that when executed by one or more processors result in the following operations comprising:
- receive, by a memory controller, an active/idle signal from partition control circuitry;
- wherein the partition control circuitry to control at least one partition of a memory array and wherein the active/idle signal has a state indicative of one of an active state or an idle state of the partition control circuitry;
- receive, by the memory controller, a memory access command;
- determine, by the memory controller, if the memory access command is legitimate;
- and
- enable, by the memory controller for the partition control circuitry, a clock signal if the memory access command is legitimate and if the active/idle signal is in an idle state.
Dependencies are inferred from the claim text.