US 10,095,421 B2 · Hybrid memory module bridge network and buffers

Abstract

Systems, apparatuses, and methods for implementing a hybrid memory module bridge network and buffers are disclosed. A system includes one or more host processors and multiple memory modules. Each memory module includes a relatively low pin count, high-bandwidth serial link to one or more other memory modules to perform inter-memory data transfers without consuming host-memory bandwidth. In one embodiment, a first memory module acts as a cache and a second memory module acts as the main memory for the system. The traffic between the host and the first memory module utilizes a first interface, and the cache traffic between the first and second memory modules utilizes a second interface. Cache line fill and writeback transfers between the first and second memory modules occur in parallel with timing-critical cache demand accesses from the host, in a latency-tolerant and buffered manner, without interfering with the cache demand accesses.

Claims20

Dependent claims

A system comprising:

a first memory module;
a second memory module coupled to the first memory module via a first interface;
and
a host processor coupled to the first memory module via a second interface different from the first interface, wherein the host processor is configured to cache data in the first memory module, and wherein the first memory module is external to the host processor;
wherein the system is configured to:
transfer data between the host processor and the first memory module via the second interface;
transfer data between the first memory module and the second memory module via the first interface without consuming bandwidth on the second interface;
and
send a retry signal from the first memory module to the host processor responsive to the host processor requesting data that is not stored in the first memory module, wherein the retry signal causes the host processor to resend a request to the first memory module at a later point in time.

6 more elements

A method comprising:

transferring data between a host processor and a first memory module via a second interface, wherein the first memory module is external to the host processor;
transferring data between the first memory module and a second memory module via a first interface without consuming bandwidth on the second interface;
caching data in the first memory module by the host processor;
and
sending a retry signal from the first memory module to the host processor responsive to the host processor requesting data that is not stored in the first memory module, wherein the retry signal causes the host processor to resend a request to the first memory module at a later point in time.

2 more elements

Dependencies are inferred from the claim text.

Hybrid memory module bridge network and buffers

Life of this patent

Hybrid memory module bridge network and buffers

Life of this patent

Abstract

Claims20