Memory system with address translation between a logical address and a physical address

#Embodiments described herein relate generally to a memory system.

#A memory system comprising a nonvolatile memory and a controller for controlling the nonvolatile memory has a translation table for resolving a logical address from a host to a physical address of the nonvolatile memory. The translation table is read from the nonvolatile memory, and is temporarily stored into a cache memory in the memory system. Generally, data transfer rate of the cache memory is higher than that of the nonvolatile memory.

#FIG. 1 is a figure illustrating a memory system according to an embodiment.

#FIG. 2A and FIG. 2B are figures, each exemplarily illustrating a change in region size.

#FIG. 3 and FIG. 4 are figures, each illustrating cluster-region relations.

#In general, according to one embodiment, a memory system which is connectable to a host, the memory system comprises: a first memory as a nonvolatile memory storing information associated with an address translation between a logical address and a physical address; a second memory temporarily storing a part of the information at least; a first controller executing a read operation and a write operation of the information for the second memory in a first data unit, the first data unit being changeable and being a data size of one of regions obtained by dividing in a first address space, the part of the information at least stored in the first memory; and a second controller executing a read operation and a write operation of the information for the first memory in a second data unit different from the first data unit.

#(Embodiments)

#FIG. 1 illustrates a memory system in one embodiment.