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US 10,095,300 B2Granted
Independent power control of processing cores
AssigneeIntel Corporation
InventorsStephen H. Gunther, Edward A. Burton, Anant Deval, Stephan Jourdan, Robert Greiner, Michael Cornaby
Life of this patent
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Abstract
Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
Claims20
A processor comprising:
- a first core integrated on a semiconductor die;
- a second core integrated on the semiconductor die;
- and
- a power controller integrated on the semiconductor die to control power consumption of the first core in response to a combination of operating conditions of the first core including a thermal condition, wherein the power controller is to control a first clock modification unit integrated on the semiconductor die to provide a clock signal to the first core and a first voltage modification unit integrated on the semiconductor die to provide a first voltage to the first core, and control a second voltage modification unit integrated on the semiconductor die to provide a second voltage, different from the first voltage, to the second core, wherein the power controller is to place the first core in a low power state while the second core is in an active state.
1 more element
A non-transitory machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
- receiving a first signal in a first power controller associated with a first core of a multicore processor, the first signal indicating a first operating condition of the first core;
- and
- changing a power state of the first core to a first power state in response to detection of a combination of operating conditions of the first core including the first operating condition and a thermal condition while a second core of the multicore processor is in a second power state different from the first power state, the second power state comprising an active power state, wherein changing the power state of the first core includes adjusting a first clock modification circuit of the first core and a first voltage modification circuit of the first core, the first voltage modification circuit to lower a voltage of the first core to a minimum level at which state of the first core is retained.
A system comprising:
- a multi-core processor comprising:
- a first core associated with a first phase lock loop (PLL) and a first voltage modification unit;
- a second core associated with a second PLL and a second voltage modification unit;
- a memory controller to interface with a memory;
- a first power control logic associated with the first core to control the first PLL to adjust a first clock frequency for the first core and to adjust the first voltage modification unit;
- and
- a second power control logic associated with the second core to control the second PLL to adjust a second clock frequency for the second core independently from the first clock frequency and to adjust the second voltage modification unit independently of the first voltage modification unit based on a combination of conditions of the second core including a thermal condition, wherein the first power control logic is to cause the first core to be in an active power state while the second core is in a low power state, wherein the first voltage modification unit is to provide a first voltage to the first core in the active power state and the second voltage modification unit is to provide a second voltage to the second core in the low power state, the first voltage different from the second voltage;
- and
- the memory coupled to the multi-core processor.
6 more elements
Dependencies are inferred from the claim text.