Ladder circuitry for multiple load regulation

A voltage regulator circuit for regulating output voltages across a plurality of loads at a plurality of output nodes, the output nodes including at least a first node, a second node, and a third node, a first load coupled between a first output voltage at the first node and a second output voltage at the second node, and a second load coupled between the second output voltage at the second node and the third node, the voltage regulator circuit comprising:

• a first stage including a first voltage controlled oscillator coupled to a first reference voltage and configured to output a first clock signal to the first load;
• and
• a second stage coupled in series with the first stage, the second stage including:
• an error amplifier coupled to a second reference voltage at a first input terminal and the second output voltage at a second input terminal, and configured to generate a control signal at an output terminal based on a comparison between the second output voltage and the second reference voltage, the control signal at a first polarity responsive to the second output voltage being greater than the second reference voltage and at a second polarity responsive to the second output voltage being less than the second reference voltage;
• a second voltage controlled oscillator configured to adjust a second clock signal output to the second load, the second voltage controlled oscillator decreasing a frequency of the second clock signal responsive to the control signal at the first polarity and increasing the frequency of the second clock signal responsive to the control signal at the second polarity to regulate the second output voltage at the second node.