Shift register and driving method thereof, gate driving device

A shift register, comprising:

• an input module coupled to an input signal end and a pull-up control node, and configured to, according to an input signal from the input signal end, provide the input signal to the pull-up control node;
• a reset module coupled to a reset signal end, a first voltage signal end and the pull-up control node, and configured to, according to a reset signal from the reset signal end, provide a first voltage signal from the first voltage signal end to the pull-up control node to reset a voltage of the pull-up control node;
• a pull-up module coupled to a first clock signal input end, the pull-up control node, an output signal end and a cascade node, and configured to, according to the voltage of the pull-up control node, provide a first clock signal from the first clock signal input end to the cascade node;
• a control module coupled to a second clock signal input end, the pull-up control node, a pull-down control node, and the first voltage signal end, and configured to, according to a second clock signal from the second clock signal input end and the voltage of the pull-up control node, control a voltage of the pull-down control node;
• a pull-down module coupled to the pull-up control node, the pull-down control node, the first voltage signal end and the output signal end, and configured to, according to the voltage of the pull-down control node, provide the first voltage signal from the first voltage signal end to the pull-up control node and the output signal end to reset the voltage of the pull-up control node and the voltage of the output signal end;
• an output gating module coupled to the cascade node, the output signal end and a control signal end, and configured to, according to a control signal from the control signal end, provide a voltage of the cascade node to the output signal end as an output signal;
• and
• an output pull-down module coupled to the first voltage signal end, a start signal input end and the output signal end, and configured to, according to a start signal from the start signal input end, provide the first voltage signal from the first voltage signal end to the output signal end;
• wherein the first clock signal and the second clock signal have opposite phases.