On-the-fly test and debug logic for ATPG failures of designs using on-chip clocking
AssigneeSTMicroelectronics International N.V.
InventorDanish Hasan Syed
Life of this patent
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Abstract
A system disclosed herein includes an on-chip clock controller (OCC) circuit receiving a test pattern and responsively generating output clock pulses in response to the test pattern. An OCC test circuit is coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs. A test output logic circuit is configured to receive the OCC test outputs from the OCC test circuit. A debug controller is operable to configure the test output logic circuit to output the OCC test outputs.
Claims20
A system, comprising:
- an on-chip clock controller (OCC) circuit configured to receive a test pattern and generate output clock pulses in response to the test pattern;
- an OCC test circuit coupled to the OCC circuit and configured to detect data corresponding to output clock pulses generated by the OCC controller circuit and generate corresponding OCC test outputs;
- a test output logic circuit configured to receive the OCC test outputs from the OCC test circuit;
- and
- a debug controller operable to configure the test output logic circuit to output the OCC test outputs.
A tester for a device under test comprising:
- an on-chip clock controller (OCC) circuit configured to receive a test pattern and generate output clock pulses in correspondence therewith;
- an OCC test circuit coupled to the OCC circuit, configured to detect whether the OCC circuit has actually generated the output clock pulses, and to generate OCC test outputs as a function thereof;
- at least one additional test circuit configured to detect failures within the device under test and generate a status signal as a function thereof;
- a test output logic circuit configured to receive the OCC test outputs and the status signal;
- and
- a debug controller operable to configure the test output logic circuit to selectively output the OCC test outputs or the status signal.
Dependencies are inferred from the claim text.