Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design

A system for verifying graph-driven verification and debugging of an electronic design, comprising:

• one or more modules, at least one of which is stored in part or in whole in memory and comprises at least one processor including one or more processor cores executing one or more threads in a computing system;
• a non-transitory computer accessible storage medium storing thereupon program code that includes a sequence of instructions that, when executed by the at least one processor, causes the at least one processor at least to:
• identify a pair of interest corresponding to a target signal comprising a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof;
• identify a boundary for relevant driver identification (RDI) operations;
• determine a plurality of candidate drivers at least by performing one or more RDI operations for the target signal based at least in part upon the boundary for the electronic design or the portion thereof based in part or in whole upon likelihood of relevancy to the pair;
• reducing the plurality of candidate drivers to a reduced number of contributing drivers at least by performing one or more analyses;
• generate, with a debug graph construction module stored at least partially in memory and functioning in conjunction with at least one computer processor, a debug display in a user interface, wherein the debug display includes and presents the reduced number of contributing drivers, at least one of the one or more RDI operations pertaining to the reduced number of contributing drivers, and corresponding source code segments pertaining to the to a user in the user interface;
• and
• ready the electronic design or a portion thereof for manufacturing at least by performing one or more verification or sign-off tasks to repair the electronic design or a portion thereof that is further integrated with the debug display in the user interface.

An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a set of acts for graph-driven verification and debugging of an electronic design, the set of acts comprising:

• identifying a pair of interest comprising a target signal and a clock cycle or an event associated with the target signal from a verification or simulation result of an electronic design or a portion thereof;
• identifying a boundary for relevant driver identification (RDI) operations;
• determining a plurality of candidate drivers at least by performing one or more RDI operations for the target signal based at least in part upon the boundary for the electronic design or the portion thereof based in part or in whole upon likelihood of relevancy to the pair;
• reducing the plurality of candidate drivers to a reduced number of contributing drivers at least by performing one or more analyses;
• generating, with a debug graph construction module stored at least partially in memory and functioning in conjunction with at least one computer processor, a debug display in a user interface, wherein the debug display includes and presents the reduced number of contributing drivers, at least one of the one or more RDI operations pertaining to the reduced number of contributing drivers, and corresponding source code segments pertaining in the user interface to a user;
• and
• readying the electronic design or a portion thereof for manufacturing at least by performing one or more verification or sign-off tasks to repair the electronic design or a portion thereof that is further integrated with the debug display in the user interface.