High capacity I/O (input/output) cells
AssigneeNXP USA, Inc.
InventorsDavid R. Tipple, Alistair J. Gorman, Anis M. Jarrar
Life of this patent
Estimating the term…
Abstract
A wafer structure has a plurality of semiconductor die. Each semiconductor die includes circuitry, a test pad for use in testing the circuitry, and a plurality of external pins. The test pad includes first, second, third, and fourth metal lines, a via, and a metal cover that receives a probe. The first and second metal lines are in a first metal layer and run in parallel, are insulated from each other, and are adjacent. The third and fourth metal lines are in a second metal layer run in parallel, are insulated from each other, and run orthogonal to the first and second metal lines. The first via is coupled to the first metal line and the third metal line. One or more external pins are connected to the metal cover.
Claims20
A wafer structure having a plurality of semiconductor die, wherein each semiconductor die comprises:
- circuitry;
- and
- a test pad for use in testing the circuitry, the test pad comprising:
- a first metal line and a second metal line in a first metal layer wherein the first and second lines run in parallel with each other, are insulated from each other, and are adjacent to each other, wherein the second metal line widens and narrows in parallel with the first metal line whereby enhancing structural integrity of an area under the test pad;
- a third metal line and a fourth metal line in a second metal layer, wherein the second metal layer is at a different level from the first metal layer, and the third and fourth metal lines run in parallel with each other, are insulated from each other, are adjacent to each other, and run orthogonal to the first metal line and the second metal line;
- a first via connected to the first metal line and the third metal line;
- a metal cover over a portion of the test pad that is for receiving a probe;
- and
- one or more external pins connected to the metal cover.
A method of forming a test pad on a semiconductor die, comprising:
- after forming circuitry in a plurality of interconnect layers using a first plurality of metal layers, forming a first metal line and a second metal line using a first higher metal layer, wherein the first metal line and the second metal line have alternating narrow portions of a first width and wide portions of a second width greater than the first width, run in parallel with each other, and are insulated from each other, wherein the second metal line widens and narrows in parallel with the first metal line whereby enhancing structural integrity of an area under the test pad;
- after forming the first metal line and the second metal line, forming a third metal line and a fourth metal line using a second higher metal layer, wherein the third metal line and the fourth metal line have alternating narrow portions of a third width and wide portions of a fourth width greater than the third width, run in parallel with each other, and are insulated from each other;
- forming a via between the first metal line and the third metal line using the second higher metal layer;
- and
- forming a conductive cover layer over the third and fourth metal lines for receiving a probe and contacting the third metal line to the conductive cover layer.
Dependencies are inferred from the claim text.