Repairable semiconductor memory device and test methods for the same

Abstract

A repair device and a semiconductor device including the same are disclosed, which relate to a technology for storing failure information in a fuse circuit during a test operation. The repair device includes a test circuit configured to test data received from a cell array in response to a test signal, and output a failure signal when a failure occurs. The repair device also includes a count circuit configured to output a counting signal by counting the failure signal, a column failure decision circuit configured to determine whether a column failure occurs in response to the counting signal, and output a write enable signal. Further, the repair device includes a fuse controller configured to output a failed column address in response to the counting signal when the write enable signal is activated, and a column fuse circuit configured to sequentially store the column address.

Dependencies are inferred from the claim text.