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US 10,090,038 B2Granted
Semiconductor memory device for deconcentrating refresh commands and system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorDong Hak Shin
Life of this patent
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Abstract
A memory device includes a buffer memory configured to receive commands from a memory controller via first to Nth channels, wherein N denotes an integer which is equal to or greater than ‘2’; and first to Nth core memories each connected to the buffer memory via one of the first to Nth channels. The buffer memory may deconcentrate refresh commands corresponding to the first to Nth core memories, based on a number of commands input during a specific time.
Claims20
A memory system comprising:
- a memory controller configured to transmit refresh commands through first to Nth independent channels in parallel, N being an integer equal to or greater than two;
- a buffer-die configured to:
- receive the refresh commands through the first to Nth independent channels;
- determine whether to skip a portion of the refresh commands based on a number of the refresh commands which are received by the buffer-die during a specific period;
- and
- skip output of the portion of the refresh commands according to a result of the determine;
- and
- first to Nth core-dies stacked on the buffer-die and electrically connected to the buffer-die through through-silicon vias (TSVs), each of the first to Nth core-dies being allocated to a corresponding independent channel, the core-dies being configured to receive the output refresh commands from the buffer-die for performing refresh operations of the core-dies,
- wherein the refresh operations performed by the core-dies are deconcentrated as a result of the skip of the output of the portion of the refresh commands.
6 more elements
A memory system comprising:
- a memory controller configured to transmit refresh commands through first to Nth independent channels in parallel, N being an integer equal to or greater than two;
- a buffer-die configured to:
- receive the refresh commands through the first to Nth independent channels;
- determine delaying a portion of the refresh commands based on a number of the refresh commands which are received by the buffer-die during a specific period;
- delay the refresh commands according to a result of the determine;
- and
- output delayed refresh commands which are generated by delaying the refresh commands;
- and
- first to Nth core-dies stacked on the buffer-die and electrically connected to the buffer-die through through-silicon vias (TSVs), each of the first to Nth core-dies being allocated to corresponding independent channel, the core-dies being configured to receive the delayed refresh commands from the buffer-die for performing refresh operations of the core-dies,
- wherein the refresh operations performed by the core-dies are deconcentrated as a result of delaying a portion of refresh operations requested by the refresh commands,
- wherein the memory controller includes a plurality of selectors, where each selector outputs one of the delayed refresh commands and a command other than a refresh command without delay, in response to a command selection signal.
8 more elements
A refreshing method of a memory device which includes a buffer-die and a plurality of core-dies, the method comprising:
- receiving, by the buffer-die, a plurality of refresh commands through first to Nth independent channels in parallel, N being an integer equal to or greater than two;
- determining, by the buffer-die, whether to skip a portion of the plurality of refresh commands based on the number of the refresh commands received during a specific period;
- skipping, by the buffer-die, transmission of the portion of the refresh commands according to a result of the determining;
- and
- performing refresh operations, by the core-dies, upon receiving the refresh commands,
- wherein the refresh operations are deconcentrated by the skipping of the transmission of the portion of the refresh commands.
3 more elements
Dependencies are inferred from the claim text.