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US 10,084,570 B2Granted
System and method for line coding
AssigneeRockley Photonics Limited
InventorsGuy Regev, Daniel Brunina, Nathan Farrington, Thomas Pierre Schrans
Life of this patent
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Abstract
A system and method for line coding of data. A serial transmitter includes a forward error correction encoding circuit followed by a bit conditioning circuit. The bit conditioning circuit counts the lengths of runs of consecutive identical digits and, when the count reaches a threshold, flips a bit. A serial receiver receives the data from the serial transmitter. The serial receiver includes a forward error correction decoding circuit, which re-flips bits flipped by the bit conditioning circuit of the serial transmitter.
Claims10
A system comprising:
- a serial transmitter having a transmitter input and a transmitter output, the serial transmitter comprising:
- a forward error correction encoding circuit having an input connected to the transmitter input, and an output;
- and
- a bit conditioning circuit having an input connected to the output of the forward error correction encoding circuit, the bit conditioning circuit comprising a bit flipping circuit configured to selectively invert a current bit, the bit conditioning circuit being configured to limit, in data transmitted through the transmitter output, a maximum run length of consecutive identical bits,
- wherein the bit conditioning circuit further comprises a continuous identical digit counting circuit configured:
- to count a number of continuous identical bits including the current bit, and
- to cause the bit flipping circuit to flip the current bit when the number of continuous identical bits including the current bit exceeds a first threshold,
- wherein the bit conditioning circuit is further configured to limit a DC imbalance of the data transmitted through the transmitter output, and
- wherein the bit conditioning circuit further comprises a running disparity counter configured:
- to keep a running count of the difference between the number of zero bits transmitted and the number of one bits transmitted, and
- to cause the bit flipping circuit to flip a bit when the running count exceeds a second threshold.
8 more elements
A serial link, comprising:
- a serial transmitter having a transmitter input and a transmitter output;
- and
- a serial receiver having a receiver input connected to the serial transmitter through a serial channel;
- the serial transmitter comprising:
- a forward error correction encoding circuit having an input connected to the transmitter input, and an output;
- and
- a bit conditioning circuit having an input connected to the output of the forward error correction encoding circuit, the bit conditioning circuit comprising a bit flipping circuit configured to selectively invert a current bit, the bit conditioning circuit being configured to limit, in data transmitted through the transmitter output, a maximum run length of consecutive identical bits,
- wherein the serial receiver comprises a forward error correction decoding circuit,
- wherein the bit conditioning circuit further comprises a continuous identical digit counting circuit configured:
- to count a number of continuous identical bits including the current bit, and
- to cause the bit flipping circuit to flip the current bit when the number of continuous identical bits including the current bit exceeds a first threshold,
- wherein the bit conditioning circuit is further configured to limit a DC imbalance of the data transmitted through the transmitter output, and
- wherein the bit conditioning circuit further comprises a running disparity counter configured:
- to keep a running count of the difference between the number of zero bits transmitted and the number of one bits transmitted, and
- to cause the bit flipping circuit to flip a bit when the running count exceeds a second threshold.
12 more elements
Dependencies are inferred from the claim text.