Vertical trench routing in a substrate
AssigneeIntel Corporation
InventorsJackson Kong, Bok Eng Cheah, Khang Choong Yong, Howard L. Heck, Kuan-Yu Chen
Life of this patent
Estimating the term…
Loading patent…
AssigneeIntel Corporation
InventorsJackson Kong, Bok Eng Cheah, Khang Choong Yong, Howard L. Heck, Kuan-Yu Chen
Estimating the term…
An interconnect topology that includes vertical trench routing in a substrate is disclosed. In one embodiment, the interconnect comprises a substrate having a plurality of layers including a first ground plane layer; a pair of signal conductors that form a differential signal pair, each conductor of the pair of signal conductors having a first portion and a second portion, the second portion extending from the first portion into at least one of the plurality of layers, wherein width of the second portion is less than width of the first portion; and wherein the first ground plane layer is only a first partial layer and has a first void region that is closer to the pair of signal conductors than the first partial layer.
An electrical interconnect comprising:
An electrical interconnect comprising:
Dependencies are inferred from the claim text.