Semiconductor device and electronic device

A semiconductor device comprising:

• memory elements arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more memory elements each including a first transistor, a second transistor, and a first capacitor;
• a first circuit;
• and
• a second circuit,
• wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor,
• wherein the gate electrode of the second transistor is electrically connected to one electrode of the first capacitor,
• wherein the other electrode of the first capacitor is electrically connected to a first wiring provided in each row,
• wherein a gate electrode of the first transistor is electrically connected to a second wiring provided in each row,
• wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a third wiring provided in each column,
• wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a fourth wiring provided in each column,
• wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a fifth wiring provided in each column,
• wherein the first wiring is capable of supplying a different potential to each row,
• wherein the fifth wirings electrically connected to the memory elements in the first to (m−1)th columns are each electrically connected to the first circuit,
• wherein the fifth wiring electrically connected to memory elements in an m-th column is electrically connected to a first power supply line,
• wherein one input terminal of the second circuit is electrically connected to the fifth wirings electrically connected to the memory elements in the first to (m−1)th columns and the first circuit through a first current mirror circuit, and
• wherein the other input terminal of the second circuit is electrically connected to the fifth wiring electrically connected to the memory elements in the m-th column and the first circuit through a second current mirror circuit.