US 10,074,667 B1Granted

Semiconductor memory device

AssigneeToshiba Memory Corporation

InventorsKazuyuki Higashi, Kazumichi Tsumura, Ryota Katsumata, Fumitaka Arai

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.

Claims20

Dependent claims

A semiconductor memory device, comprising:

a first memory cell array layer having a first surface, a second surface opposite to the first surface, a first memory cell array region in which a first plurality of memory cells is 3-dimensionally arrayed, and a first surface wiring layer and a second surface wiring layer at the first surface and the second surface, respectively, and connected to the first plurality of memory cells;
and
a second memory cell array layer having a third surface, a fourth surface opposite the third surface, a second memory cell array region in which a second plurality of memory cells is 3-dimensionally arrayed, and a third surface wiring layer and the fourth surface wiring layer at the third surface and the fourth surface, respectively, and connected to the second plurality of memory cells, wherein
the first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other, and the first and second memory cell array regions overlap each other as viewed from a direction orthogonal to the first surface.

1 more element

A semiconductor memory device, comprising:

a peripheral circuit layer that includes a circuit substrate, a control circuit formed on a circuit formation surface of the circuit substrate, and a circuit-side wiring layer formed at the circuit formation surface and electrically connected to the control circuit;
a first memory cell array layer having a first surface, a second surface opposite to the first surface, a first memory cell array region in which a first plurality of memory cells is 3-dimensionally arrayed, a first signal line extraction electrode electrically connected to the first plurality of memory cells, a first external connection electrode disposed outside the first memory cell array region, as viewed in a direction orthogonal to the first surface, and electrically connected to the control circuit, a first surface wiring layer at the first surface and connected to the first signal line extraction electrode, and a second surface wiring layer at the second surface and connected to the first external connection electrode;
and
a second memory cell array layer having a third surface, a fourth surface opposite to the third surface, a second memory cell array region in which a second plurality of memory cells is 3-dimensionally arrayed, a second signal line extraction electrode electrically connected to the second plurality of memory cells, a second external connection electrode disposed outside the second memory cell array region, as viewed in the direction orthogonal to the first surface, and electrically connected to the first external connection electrode, a third surface wiring layer at the third surface and connected to the second signal line extraction electrode, and a fourth surface wiring layer at the fourth surface and connected to the second external connection electrode, wherein,
the first surface faces the peripheral circuit layer,
the circuit-side wiring layer and the first surface wiring layer are bonded to each other,
the third surface faces the first memory cell array layer, and
the second surface wiring layer and the third surface wiring layer are bonded to each other.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/688,561Filed 28 Aug 2017
Priority: JP 2017-04639510 Mar 2017
Published: US 2018/0261623 A113 Sep 2018
Granted: 11 Sep 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification26 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/20
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by three-dimensional [3D] arrangements, e.g.…
H10B 41/23
Characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels: with source and drain on different levels, e.g.…
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels