Intra prediction processor with reduced cost block partitioning and refined intra mode selection

A hardware encoder implemented in a semiconductor, comprising:

• a first block size intra mode processor to perform first intra mode searches for best intra modes for the first block size, a second block size intra mode processor to perform second intra mode searches for best intra modes for the second block size, wherein the second block size is larger than the first block size, a third block size intra mode processor to perform third intra mode searches for best intra modes for the third block size, wherein the third block size is larger than the second block size;
• a cost processor to compute cost values for the first block size, the second block size and the third block size, wherein the cost values are based upon at least one of a simplified distortion estimate utilizing an approximation technique or a simplified bit rate estimate utilizing an approximation technique;
• and
• a selective block merger processor to establish a final partition of blocks including the first block size being merged into the second block size or the third block size.