Method of speeding up output alignment in a digital phase locked loop

A method of performing output clock alignment in a digital phase locked loop wherein a controlled oscillator generates synthesizer pulses that are divided to produce output pulses at a predetermined normal spacing and time location, and wherein during an alignment procedure said output pulses are moved in time in response to a delay value obtained by comparing a phase of the output pulses with a phase applied to the controlled oscillator averaged over a number of synthesizer pulses in a feedback circuit to align said output pulses with a reference clock taking into account hardware delay, the method comprising:

• advancing a group of said output pulses during the alignment procedure to reduce the spacing between said output pulses;
• determining the delay value averaged over said group of output pulses with reduced spacing;
• generating subsequent output pulses at their normal spacing and time locations;
• and
• moving said subsequent output pulses in time by said delay value to compensate for the hardware delay.