Summer circuit including linearized load

An apparatus comprising:

• a first circuit portion including a first transistor to receive a first signal of a differential signal pair, and a second transistor to receive a second signal of the differential signal pair;
• a second circuit portion coupled to the first and second transistors and a first supply node, the second circuit portion including a first output node and a second output node to provide an output signal pair based on the differential signal pair, wherein the second circuit portion includes:
• a third transistor coupled between the first supply node and the first transistor;
• a fourth transistor coupled between the first supply node and the second transistor;
• a fifth transistor coupled between the first supply node and the first output node;
• a sixth transistor coupled between the first supply node and the second output node;
• a first resistor coupled between a gate of the fifth transistor and a node;
• and
• a second resistor coupled between a gate of the sixth transistor and the node;
• and
• a third circuit portion including a first diode-connected transistor coupled between the first output node and a second supply node, and a second diode-connected transistor coupled between the second output node and the second supply node.

An apparatus comprising:

• a first circuit included in an equalizer circuitry and to receive a first differential signal pair and generate a second differential signal pair based on the first differential signal pair, the first circuit including:
• a first circuit portion including a first transistor to receive a first signal of the second differential signal pair, and a second transistor to receive a second signal of the second differential signal pair;
• a second circuit portion including a third transistor coupled between a first supply node and a first output node to provide a first signal of the second differential pair, and a fourth transistor coupled between the first supply node and a second output node to provide a second signal of the second differential pair, the third transistor including a gate, and the fourth transistor including a gate coupled to the gate of the third transistor;
• and
• a third circuit portion including a first diode-connected transistor coupled between the first output node and a second supply node, and a second diode-connected transistor coupled between the second output node and the second supply node;
• and
• a second circuit including a pair of transistors having gates to receive the second differential signal pair from the output nodes of the first circuit, and to generate digital information based on the second differential signal pair.

An apparatus comprising:

• a first circuit included in an equalizer circuitry and to receive a first differential signal pair and generate a second differential signal pair based on the first differential signal pair, the first circuit including:
• a first circuit portion including a first transistor to receive a first signal of the second differential signal pair, and a second transistor to receive a second signal of the second differential signal pair;
• a second circuit portion including a third transistor coupled between a first supply node and a first output node to provide a first signal of the second differential pair, and a fourth transistor coupled between the first supply node and a second output node to provide a second signal of the second differential pair, the first transistor including a drain coupled to a source of the third transistor and the first output node, and the second transistor including a drain coupled to a source of the fourth transistor and the second output node;
• a third circuit portion including a first diode-connected transistor coupled between the first output node and a second supply node, and a second diode-connected transistor coupled between the second output node and the second supply node, the first and second diode-connected transistors and the third and fourth transistors having a same transistor type, wherein each of the first and second diode-connected transistors, and the third and fourth transistors has a gate coupled to a resistor;
• and
• a second circuit including a pair of transistors having gates to receive the second differential signal pair from the output nodes of the first circuit, and to generate digital information based on the second differential signal pair.

An apparatus comprising:

• conductive lines on a circuit board;
• a device located on the circuit board and coupled to the conductive lines;
• and
• a processor located on the circuit board and including a receiver coupled to the conductive lines, the receiver including a circuit, the circuit including:
• a first circuit portion including a first transistor to receive a first signal of a differential signal pair provided by the device, and a second transistor to receive a second signal of the differential signal pair;
• a second circuit portion coupled to the first and second transistors and a first supply node, the second circuit portion including a first output node and a second output node to provide an output signal pair based on the differential signal pair, wherein the second circuit portion includes:
• a first additional transistor coupled between the first supply node and the first output node, the first additional transistor including a gate:
• a second additional transistor coupled between the first supply node and the second output node, the second additional transistor including a gate coupled to the gate of the first additional transistor;
• and
• a third circuit portion including a first diode-connected transistor coupled between the first output node and a second supply node, and a second diode-connected transistor coupled between the second output node and the second supply node.