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US 10,061,541 B1Granted
Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path
AssigneeMicron Technology, Inc.
InventorJoosang Lee
Life of this patent
Estimating the term…
Abstract
A system includes multiple memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path that refreshes a first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activates a row of a second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path.
Claims20
A system comprising:
- a plurality of memory banks configured to store data, wherein the plurality of memory banks comprises a first set of memory banks and a second set of memory banks;
- an address path coupled to the plurality of memory banks, wherein the address path is configured to provide a row address to the plurality of memory banks;
- and
- a command address input circuit coupled to the address path, wherein the command address input circuit is configured to refresh the first set of memory banks via the address path and, when the command address input circuit refreshes the first set of memory banks, activate a row of the second set of memory banks to store the data or read the data from the row of the second set of memory banks via the address path, wherein the command address input circuit comprises:
- a first counter configured to store and increment a first row address of the first set of memory banks to be refreshed;
- and
- a second counter configured to store and increment a second row address of the second set of memory banks to be refreshed.
4 more elements
A system comprising:
- a register configured to store a row address;
- a plurality of memory banks configured to store data, wherein the plurality of memory banks comprises a first set of memory banks and a second set of memory banks;
- and
- a plurality of bank control blocks coupled to the plurality of memory banks, wherein the plurality of bank control blocks comprises:
- a first set of bank control blocks configured to refresh the first set of memory banks by:
- capturing the row address from the register;
- refreshing a first row of the first set of memory banks, wherein the first row is associated with the row address that was captured from the register;
- incrementing the row address that was captured from the register;
- and
- refreshing a second row of the first set of memory banks, wherein the second row is associated with the row address that was captured from the register and incremented;
- and
- a second set of bank control blocks configured to activate a third row of the second set of memory banks, and, at the same time, the first set of bank control blocks refreshes the first row of the first set of memory banks, refreshes the second row of the first set of memory banks, or a combination thereof.
9 more elements
A row address output circuit comprising:
- a first counter configured to store and increment a first row address of a first set of memory banks of a semiconductor device to be refreshed;
- a second counter configured to store and increment a second row address of the second set of memory banks of the semiconductor device to be refreshed;
- and
- a multiplexer configured to:
- receive, as inputs, the first row address from the first counter, the second row address from the second counter, a third row address associated with a first row of the first set of memory banks or a second row of the second set of memory banks to be activated, and a selection signal;
- output the first row address when the selection signal is associated with refreshing the plurality of memory banks or refreshing the first set of memory banks;
- output the second row address when the selection signal is associated with refreshing the plurality of memory banks or refreshing the second set of memory banks;
- and
- output the third row address when the selection signal is associated with activating the first row of the first set of memory banks or the second row of the second set of memory banks, wherein the first set of memory banks is configured to be refreshed during activation of the second row of the second set of memory banks, wherein the second set of memory banks is configured to be refreshed during activation of the first row of the first set of memory banks.
6 more elements
A method comprising:
- receiving a command at a semiconductor device;
- when the command is configured to refresh a plurality of memory banks of the semiconductor device, outputting a first row address of a first set of memory banks of the plurality of memory banks or a second row address of a second set of memory banks of the plurality of memory banks to be refreshed, wherein the first row address is stored in a first counter of the semiconductor device and the second row address is stored in a second counter of the semiconductor device;
- when the command is configured to separately refresh the first set of memory banks, outputting the first row address stored in the first counter;
- when the command is configured to separately refresh the second set of memory banks, outputting the second row address stored in the second counter;
- when the command is configured to activate a first row of the first set of memory banks, receiving and outputting a third row address associated with the first row, wherein the second set of memory banks is configured to be refreshed during activation of the first row of the first set of memory banks;
- and
- when the command is configured to activate a second row of the second set of memory banks, receiving and outputting a fourth row address associated with the second row, wherein the first set of memory banks is configured to be refreshed during activation of the second row of the second set of memory banks.
4 more elements
Dependencies are inferred from the claim text.