Division operations for memory

An apparatus comprising:

• a first address space of a memory array comprising a first group of memory cells coupled to a sense line and to a first number of select lines, wherein the first address space stores a dividend value;
• a second address space of the memory array comprising a second group of memory cells coupled to the sense line and to a second number of select lines, wherein the second address space stores a divisor value;
• a third address space of the memory array comprising a third group of memory cells coupled to the sense line and to a third number of select lines;
• and
• a controller configured to:
• cause a division operation to be performed by performing N number of iterations, wherein N is an integer greater than 1 and a first iteration comprises:
• copying a bit stored in the Nth memory cell of the first group of memory cells into a first memory cell of the third group of memory cells;
• and
• comparing the divisor value with the remainder value;
• and
• cause the remainder value to be stored in the third address space.

A method, comprising:

• performing, via N number of iterations, a number of division operations, wherein N is an integer greater than 1 and a first iteration comprises:
• copying a bit stored in an Nth memory cell of a number of respective first portions of a group of memory cells into respective first memory cells of a number of respective fourth portions of the group of memory cells, wherein performing the number of division operations includes using a respective number of dividend values stored in the number of respective first portions of the group of memory cells and a respective number of divisor values stored in a number of respective second portions of the group of memory cells;
• and
• comparing the respective number of divisor values with a respective number of remainder values stored in a respective number of fourth portions of the group of memory cells;
• and
• storing a respective number of quotient values resulting from the number of division operations in a number of respective third portions of the group of memory cells, wherein a number of computations used to perform each respective one of the number of division operations is the same.