Variable precision floating-point adder and subtractor
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
Estimating the term…
Abstract
An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and a far path using a dual path floating-point adder architecture depending on the difference of the exponents and on whether an addition or subtraction is being performed. The mantissa values may be left justified, while the sticky bits are right justified. The hardware for the largest mantissa can be used to support the calculations for the smaller mantissas using no additional arithmetic structures, with only some multiplexing and decoding logic.
Claims20
An integrated circuit, comprising:
- a floating-point adder that receives first and second numbers, each having a mantissa and an exponent, wherein the floating-point adder comprises:
- a mantissa alignment circuit;
- an addition circuit, wherein the mantissa alignment circuit and the addition circuit are operable in a first mode that supports a first mantissa size and are also operable in a second mode that supports a second mantissa size that is different than the first mantissa size;
- a subtraction circuit;
- a normalization circuit, wherein the subtraction circuit and the normalization circuit are also operable in the first and second modes;
- and
- a multiplexer configured to receive far path signals from the addition circuit and to receive near path signals from the normalization circuit in the first and second modes.
A method of operating a floating-point adder on an integrated circuit, wherein the method comprises:
- receiving first and second numbers each having a mantissa and an exponent;
- routing the first and second numbers to a near path when a difference in the exponents is equal to or less than a predetermined threshold;
- routing the first and second numbers to a far path when the difference in the exponents exceeds the predetermined threshold;
- operating the floating-point adder in a first mode to support a first mantissa size for the first and second numbers;
- operating the floating-point adder in a second mode to support a second mantissa size that is different than the first mantissa size;
- determining a first maximum mantissa shift amount for the first mode;
- and
- determining a second maximum mantissa shift amount that is different than the first maximum mantissa shift amount for the second mode.
An integrated circuit, comprising:
- a floating-point adder that receives first and second numbers, each having a mantissa and an exponent, wherein the floating-point adder comprises:
- a mantissa alignment circuit;
- and
- an addition circuit, wherein the mantissa alignment circuit and the addition circuit are operable in a first mode that outputs a first sum with a first mantissa size and in a second mode that outputs a second sum with a second mantissa size that is different than the first mantissa size, and wherein the difference in the first and second mantissa sizes is less than or equal to 13.
Dependencies are inferred from the claim text.