Testing multi-core integrated circuit with parallel scan test data inputs and outputs

A multi-core integrated circuit comprising:

• a set of nominally similar cores;
• pairs of test data input (TDI) and test data output (TDO) pads, and corresponding expected response input pads, that are common to the different cores of the set;
• wherein the cores are each configurable in a test mode with a plurality of scan chains, wherein similar scan chains in the different cores are connected in common to respective TDI pads and provide response signals from the different cores as functions of corresponding TDI signals applied to the respective common TDI pads;
• respective first conjunction modules for the different scan chains providing to the TDO pads respective first combined TDO signals that in the absence of defect are asserted like the response signals from corresponding chains in the different cores and like expected response signals applied to the expected response input pads for the corresponding scan chains;
• and
• respective second conjunction modules for the different scan chains providing to the TDO pads respective second combined TDO signals that in the absence of defect are de-asserted like the response signals from the corresponding chains in the different cores and like the expected response signals for the corresponding scan chains;
• and
• wherein the combined TDO signals are asserted and de-asserted differently from the expected response signals for the corresponding scan chains in the presence of a defect in at least one of the cores.