Fast settling capacitive gain amplifier circuit

A method of capacitive gain amplification to amplify an input signal by a pair of differential amplifier circuits coupled in parallel, the method comprising:

• switching in a first set of Miller capacitors between respective outputs and respective inputs of the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit;
• switching in a second set of Miller capacitors between respective outputs and respective inputs of the first output stage differential amplifier circuit during a second phase that chops a signal being amplified by the first output stage differential amplifier circuit, the switching in of the second set of Miller capacitors being to alternating inputs of the first output stage differential amplifier circuit during successive second phases;
• and
• operating both the first output stage differential amplifier circuit and the second output stage differential amplifier circuit during the second phase, the second output stage differential amplifier circuit having inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.

A capacitive gain amplifier circuit, comprising:

• a first output stage differential amplifier circuit, including a pair of inputs and a pair of outputs;
• a first pair of Miller capacitors, selectively switched in between respective outputs and respective inputs of the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit, and selectively switched out from respective outputs and respective inputs of the first output stage differential amplifier circuit during a second phase to retain electrical charge on the first pair of Miller capacitors between successive first phases;
• a second pair of Miller capacitors, selectively switched in between respective outputs and respective inputs of the first output stage differential amplifier circuit during a separate second phase that chops a signal being amplified by the first output stage differential amplifier circuit, the second pair of Miller capacitors being selectively switched in to alternating inputs of the first output stage differential amplifier circuit during successive second phases in correspondence with the chopping of the signal being amplified by the first output stage differential amplifier circuit, and selectively switched out from respective outputs and respective inputs of the first output stage differential amplifier circuit during the first phase to retain electrical charge on the second pair of Miller capacitors between successive second phases;
• and
• a second output stage differential amplifier circuit, including a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase.